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datasheet r01ds0096ej0100 rev.1.00 page 1 of 92 apr 20, 2011 rx62t group renesas mcus features 32-bit rx cpu core ? max. operating frequency: 100 mhz capable of 165 dmips in operation at 100 mhz ? single precision 32-bit ieee-754 floating point ? accumulator handles 64-bit results (for a single instruction) from 32- 32-bit operations ? multiplication and division unit handles 32- 32-bit operations (multiplication in structions take one cpu clock cycle) ? fast interrupt ? divider (fastest instructi on execution takes two cpu clock cycles) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instruc tions: ultra-compact code ? background jtag debugging pl us high-speed tracing operating voltage ? single 3.3- or 5-v supply; 5- v analog supply is possible with 3.3-v products low-power design and architecture ? four low-power modes on-chip main flash me mory, no wait states ? 100-mhz operation, 10-ns read cycle ? no wait states for reading at full cpu speed ? 64-kbyte/128-kbyte/256-kbyte capacities ? for instructions and operands ? user code programmable via the sci or jtag on-chip data flash memory ? max. 32 kbytes, reprogr ammable up to 30,000 times ? erasing and programming impose no load on the cpu. on-chip sram, no wait states ? 8-kbyte/16-kbyte sram ? for instructions and operands dma ? dtc: the single unit is capable of transfer on multiple channels reset and supply management ? power-on reset (por) ? low voltage detection (l vd) with voltage settings clock functions ? external crystal oscillator or internal pll for operation at 8 to 12.5 mhz ? internal 125-khz loco for the iwdt ? detection of main oscill ator stoppage (for iec 60730 compliance) independent watchdog timer (for iec60730compliance) ? 125-khz loco clock operation ? software is incapable of stopping the robust wdt. up to 7 co mmunication s interfaces ? 1: can (compliant with iso11898-1), incorporating 32 mailboxes ? 3: scis, with asynchronous mode (incorporating noise cancellation), clock-synchronous mode, and smart-card interface mode ? 1: i2c bus interface, capable of smbus operation ? 1: rspi ? 1: lin up to 16 16-bit timers ? 8: 16-bit mtu3: 100-mhz operation, input capture, output compare, two three- phase complementary pwm output channels, complementary pwm imposing no load on the cpu, phase-counting mode ? 4: 16-bit gpt: 100-mhz operati on, input capture, output compare, four complement ary single-phase pwm output channels, or one three-phase complementary pwm output channel and one si ngle-phase complementary pwm output channel, comp lementary pwm imposing no load on the cpu, operation linked with comparator (for counting and control of pwm- signal negation), detection of abnormal oscillation frequencies (for iec 60730 compliance) ? 4: 16-bit cmt three a/d converter units for 1-mhz operation, for a total of 20 channels ? three units are ca pable of simultaneous sampling on seven channels ? self diagnosis (for iec60730 compliance) ? 8: two 12-bit adc units: three sample-and-hold circuits, double data registers, amplifier, comparator ? 12: single 10-bit adc unit crc (cyclic redundancy check) calculation unit ? monitoring of data being transferred (for iec 60730 compliance) ? monitoring of data in memory (for iec 60730 compliance) up to 61 input?output port s and up to 21 input-only ports ? port registers: monitoring of output ports (for iec 60730 compliance) operating temp. range ? ?40 ?c to +85 ?c plqp0112ja-a 2020mm, 0.65mm pitch plqp0100kb-a 1414mm, 0.5mm pitch plqp0080ja-a 1414mm, 0.65mm pitch plqp0064kb-a 1010mm, 0.5mm pitch 100-mhz 32-bit rx mcus, fpu, 165 dmips, 12-bit adc (3 s/h circuits, double data register, amplifier, comparator): two unit s, 10-bit adc one unit, the three adc units are capable of simultaneous 7-ch. sampling, 100-mhz pwm (two three-phase complementary channels and four single-phase complementary channels or three three-phase complementary channels and one single-phase complementary channel) r01ds0096ej0100 rev.1.00 apr 20, 2011
r01ds0096ej0100 rev.1.00 page 2 of 92 apr 20, 2011 rx62t group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications in outline, and table 1.2 lists the functions of products. table 1.1 outline of specifications (1 / 5) classification module/function description cpu cpu ? maximum operating frequency: 100mhz ? 32-bit rx cpu ? minimum instruction execution time: one instruction per state (cycle of the system clock) ? address space: 4-gbyte linear ? register set of the cpu ? general purpose: sixteen 32-bit registers ? control: nine 32-bit registers ? accumulator: one 64-bit register ? basic instructions: 73 ? floating-point instructions: 8 ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement ? instructions: little endian ? data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32 x 32 ? 64 bits ? on-chip divider: 32 / 32 ? 32 bits ? barrel shifter: 32 bits fpu ? single precision (32-bit) floating point ? data types and floating-point exceptions in conformance with the ieee754 standard memory rom ? rom capacity: 256 kbytes (max.) ? two on-board programming modes ? boot mode (the user mat is programmable via the sci) ? user program mode ? off-board programming ? a prom programmer can be used to program the user mat. ram ? ram capacity: 16 kbytes (max.) data flash ? data flash capacity: 32 kbytes (max.) ? supports background operations (bgo) mcu operating mode ? single-chip mode clock clock generation circuit ? one circuit: main clock oscillator ? internal oscillator: low-speed on-ch ip oscillator dedicated to iwdt ? structure of a pll frequency synthesizer and frequency divider for selectable operating frequency ? oscillation stoppage detection ? independent frequency-division and multiplication settings for the system clock (iclk) and peripheral module clock (pclk) ? the cpu and system sections such as other bus masters, mtu3, and gpt run in synchronization with the system clock (iclk): 8 to 100 mhz. ? peripheral modules run in sy nchronization with the peripheral module clock (pclk): 8 to 50 mhz reset pin reset, power-on reset (automatic power-on reset when the power is turned on), voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, and deep software standby reset voltage detection circuit (lvd) when the voltage on vcc falls below the voltage detection level (vdet), an internal reset or internal interrupt is generated. l ow power consumption low p o wer consumption facilities ? module stop function ? four low power consumption modes ? sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode
r01ds0096ej0100 rev.1.00 page 3 of 92 apr 20, 2011 rx62t group 1. overview interrupt interrupt control unit (icu) ? peripheral function interrupts: 101 sources ? external interrupts: 9 (nmi and irq0 to irq7 pins) ? non-maskable interrupts: 3 (the nmi pin, oscillation stop detection interrupt, and voltage- monitoring interrupt) ? 16 levels specifiable for the order of priority data transfer data transfer controller (dtc) ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, external interrupts, and interrupt requests from peripheral functions i/o ports programmable i/o ports i/o port pins for devices in the 112-pi n lqfp/100-pin lqfp/80-pin lqfp/64-pin lqfp ? i/o: 61/55/44/37 ? input only: 21/21/13/9 ? open-drain outputs: 2/2/2/2 (i 2 c bus interface pins) ? large-current outputs: 12/12/6/6(0) (mtu3 and gpt pins) the 5-v version of the 64-pin product does not have large-current outputs. ? reading out the states of pi ns is always possible. timers multi-function timer pulse unit 3 (mtu3) ? 16 bits x 8 channels ? up to 24 pulse inputs/outputs and three pulse inputs ? select from among six to eight counter-i nput clock signals for each channel (iclk/1, iclk/4, iclk/16, iclk/64, iclk/256, iclk/1024, mtclka, mtclkb, mtclkc, mtclkd) other than channel 5, for which only four signals are available. ? 24 output compare or input capture registers ? counter clearing (clearing is synchronizable with compar e match or input capture) ? simultaneous writing to multiple timer counters (tcnt) ? input to and output from all registers in synchronization with counter operation ? buffered operation ? cascade-connected operation ? 38 kinds of interrupt source ? automatic transfer of register data ? pulse output modes toggled, pwm, complementary pwm, and reset synchronous pwm ? complementary pwm output mode outputs non-overlapping waveforms for controlling 3-phase inverters automatic specification of dead times pwm duty cycle: selectable as any value from 0% to 100% delay can be applied to requests for a/d conversion. non-generation of interrupt requests at peak or trough values of counters can be selected. double buffering ? reset-synchronous pwm mode three pwm waveforms and corresponding inverse waveforms are output with the desired duty cycles. ? phase-counting mode ? counter functionality for dead-time compensation ? generation of triggers for a/d converters ? differential timing for initiation of a/d conversion port output enable 3 (poe3) ? control of the high-impedance state of the mtu3 and gpt?s waveform output pins 5 pins for input from signal source s: poe0, poe4, poe8, poe10, poe11 initiation on detection of short-circuited out puts (detection of simultaneous switching of large-current pins to the active level) initiation by comparator-detection of analog level input to the 12-bit a/d converter initiation by oscillation-stoppage detection initiation by software ? selection of which output pins should be pl aced in the high-impedance state at the time of each poe input or comparator detection table 1.1 outline of specifications (2 / 5) classification module/function description
r01ds0096ej0100 rev.1.00 page 4 of 92 apr 20, 2011 rx62t group 1. overview timers general pwm timer (gpt) ? 16 bits x 4 channels ? counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels ? clock sources independently selectable for all channels ? 2 input/output pins per channel ? 2 output compare/input capture registers per channel ? for the 2 output compare/input capture r egisters of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. ? in output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically pwm waveforms. ? registers for setting up frame intervals on each channel (with c apability for generating interrupts on overflow or underflow) ? synchronizable operation of the several counters ? modes of synchronized operation (synchronized, or displaced by des ired times for phase shifting) ? generation of dead times in pwm operation ? through combination of three counters, generation of automatic three-phase pwm waveforms incorporating dead times ? starting, clearing, and stopping counters in re sponse to external or internal triggers ? internal trigger sources: output of the internal comparator detection, software, and compare-match ? the frequency-divided system clock (iclk) can be used as a counter clock for measuring timing of the edges of signals produced by frequency-dividing the low-speed on-chip oscillator clock signal dedicated to iwdt (to detect abnormal oscillation). compare match timer (cmt) ? (16 bits x 2 channels) x 2 units ? select from among four internal clock signals (pclk/8, pclk/32, pclk/128, pclk/512) watchdog timer (wdt) ? 8 bits x 1 channel ? select from among eight counter-input clock signals (pclk/4, pclk/64, pclk/128, pclk/512, pclk/2048, pclk/8192, pclk/32768, pclk/131072) ? switchable between watchdog timer mode and interval timer mode independent watchdog timer (iwdt) ? 14 bits x 1 channel ? counter-input clock: low-speed on-chip oscillator dedicated to iwdt communications serial communications interface (scib) ? 3 channels ? serial communications modes: asynchronous, clock synchronous, and smart-card interface ? multiprocessor communications ? on-chip baud rate generator allows selection of the desired bit rate ? choice of lsb-first or msb-first transfer ? noise cancellation (only avai lable in asynchronous mode) i 2 c bus interface (riic) ? 1 channel ? communications formats i 2 c bus format/smbus format master/slave selectable table 1.1 outline of specifications (3 / 5) classification module/function description
r01ds0096ej0100 rev.1.00 page 5 of 92 apr 20, 2011 rx62t group 1. overview communications can module (can) (as an optional function) ? 1 channel ? 32 mailboxes serial peripheral interface (rspi) ? 1 unit ? rspi transfer facility using the mosi (master out, slave in), miso (master in, slave out), ssl (slave select), and rspi clock (rspck) signals enables serial transfer through spi operation (four lines) or clock- synchronous operation (three lines) capable of handling serial transfer as a master or slave ? data formats switching between msb first and lsb first the number of bits in each transfer can be c hanged to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or re ceived in a single transfer operation (with each frame having up to 32 bits) ? buffered structure ? double buffers for both transmission and reception lin module (lin) ? 1 channel (lin master) ? supports revisions 1.3, 2.0, and 2.1 of the lin protocol a/d converter 12-bit a/d converter (s12ada) ? 12 bits (2 units x 4 channels) ? 12-bit resolution ? conversion time: 1.0 ? s per channel (in operation with a/d conversion clock adclk at 50 mhz) for avcc = 4.0 to 5.5 v 2.0 ? s per channel (in operation with a/d c onversion clock adclk at 25 mhz) for avcc0 = 3.0 to 3.6 v ? two basic operating modes single mode and scan mode ? scan mode one-cycle scan mode continuous scan mode 2-channel scan mode (input ports of the a/d unit are divided into two groups in this mode, and the activation sources are separately selectable for each group.) ? sample-and-hold function a common sample-and-hold circuit for both units is included. additionally, sample-and-hold circuit for each unit is included. (three channels per unit) ? a/d-conversion register se ttings for each input pin. ? two registers for the result of conversion are provided for a single analog input pin of each unit (an000 and an100). ? three ways to start a/d conversion conversion can be started by software, a conv ersion start trigger from a timer (mtu3 or gpt), or an external trigger signal. ? functionality for 8- or 10-bit precision output right-shifting of the results of conversion for output by two or four bits is selectable. ? self-diagnostic function the self-diagnostic function internally generat es three analog input voltages (vrefl0, vrefh0 x 1/2, vrefh0). ? amplification of input signals by a progra mmable gain amplifier (three channels per unit) amplification rate: 2.0-, 2.5-, 3.077-, 3.636-, 4.0-, 4.444-, 5.0-, 5.714-, 6.667-, 10.0-, or 13.333-times amplification (a total of 11 steps) ? window comparators (three channels per unit) table 1.1 outline of specifications (4 / 5) classification module/function description
r01ds0096ej0100 rev.1.00 page 6 of 92 apr 20, 2011 rx62t group 1. overview a/d converter 10-bit a/d converter (ada) ? 10 bits (1 unit x 12 channels) ? 10-bit resolution ? conversion time: 1.0 ? s per channel (in operation with a/d c onversion clock adclk at 50 mhz) for avcc0 = 4.0 to 5.5 v 2.0 ? s per channel (in operation with a/d conversion clock adclk at 25 mhz) for avcc = 3.0 to 3.6 v ? two basic operating modes single mode and scan mode ? scan mode one-cycle scan mode continuous scan mode ? sample-and-hold function a common sample-and-hold circuit for both units is included. ? a/d-conversion register settings for each input pin ? three ways to start a/d conversion conversion can be started by software, a conv ersion start trigger from a timer (mtu3 or gpt), or an external trigger signal. ? functionality for 8-bit precision output right-shifting the results of conversion for output by two bits is selectable. ? self-diagnostic function the self-diagnostic function internally gener ates three analog input voltages (avss, vref x 1/2, vref). crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1. ? generation of crc codes for use with l sb-first or msb-firs t communications is selectable. operating frequency iclk: 8 to 100 mhz pclk: 8 to 50 mhz power supply voltage ? 3-v version vcc = pllvcc = 2.7 to 3.6v avcc0 = avcc = 3.0 to 3.6v, or 4.0 to 5.5v vrefh0 = 3.0 to avcc0, or 4.0 to avcc0 vref = 3.0 to avcc, or 4.0 to avcc ? 5-v version vcc = pllvcc = 4.0 to 5.5v avcc0 = avcc = 4.0 to 5.5v vrefh0 = 4.0 to avcc0 vref = 4.0 to avcc operating temperature ?40 to +85 ? c packages 112-pin lqfp (plqp0112ja-a, 20x20-0.65-mm pitch) 100-pin lqfp (plqp0100kb-a, 14x14-0.5-mm pitch) 80-pin lqfp (plqp0080ja- a, 14x14-0.65-mm pitch) 64-pin lqfp (plqp0064kb-a, 10x10-0.5-mm pitch) table 1.1 outline of specifications (5 / 5) classification module/function description
r01ds0096ej0100 rev.1.00 page 7 of 92 apr 20, 2011 rx62t group 1. overview note 1. o: supported, ? : not supported note 2. * for the mtu and gpt, the number of pins will differ with the package. see the list of pins and pin functions for details. in addition, the can module is an optional function. table 1.2 functions of rx62t group products functions rx62t group pin number 112 pin 100 pin 80 pin 64 pin data transfer data transfer controller (dtc) o interrupt control unit (icu) input on the nmi pin o input on the irq pins o (8) o (4) timers multi-function timer pulse unit 3 (mtu3) o o * general pwm timer (gpt) o o * port output enable 3 (poe3) o (poe pins: 5) o (poe pins: 3) compare match timer (cmt) o watchdog timer (wdt) o independent watchdog timer (iwdt) o communication function serial communications interface (sci) o i 2 c bus interface (riic) o can module (can) (as an optional function) o lin module (lin) o serial peripheral interface (rspi) o 12-bit a/d converter (s12ada) o (4 ch. x 2 units) simultaneous sampling on three channels o (2 units) programmable gain amplifier o (3 ch. x 2 units) window comparator o (3 ch. x 2 units) 10-bit a/d converter (ada) o (12 ch.) o (4 ch.) ? crc calculator (crc) o i/o ports i/o pins 61 55 44 37 input pins 21 21 13 9 package lqfp2020 (0.65-mm pitch) lqfp1414 (0.5-mm pitch) lqfp1414 (0.65-mm pitch) lqfp1010 (0.5-mm pitch)
r01ds0096ej0100 rev.1.00 page 8 of 92 apr 20, 2011 rx62t group 1. overview 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product part no. table 1.3 list of products group part no. package operating frequency (max.) rom capacity ram capacity data flash operating voltage can package type pin pitch package code vcc/ pllvcc avcc/ avcc0 rx62t r5f562taadfh lqfp2020-112 0.65 mm plqp0112ja-a 100 mhz 256 kbytes 16 kbytes 32k bytes 4.0 to 5.5 v 4.0 to 5.5 v supp orted r5f562taadfp lqfp1414-100 0.5 mm plqp0100kb-a r5f562taadff lqfp1414-80 0.65 mm plqp0080ja-a r5f562taadfm lqfp1010-64 0.5 mm plqp0064kb-a r5f562t7adfh lqfp2020-112 0.65 mm plqp0112ja-a 128 kbytes 8 kbytes 8k bytes r5f562t7adfp lqfp1414-100 0.5 mm plqp0100kb-a r5f562t7adff lqfp1414-80 0.65 mm plqp0080ja-a r5f562t7adfm lqfp1010-6 4 0.5 mm plqp0064kb-a r5f562t6adff lqfp1414-80 0.65 mm plqp0080ja-a 64 kbytes 8 kbytes r5f562t6adfm lqfp1010-6 4 0.5 mm plqp0064kb-a r5f562tabdfh lqfp2020-112 0.65 mm plqp0112ja-a 256 kbytes 16 kbytes 32k bytes 2.7 to 3.6 v 3.0 to 3.6 v or 4.0 to 5.5 v r5f562tabdfp lqfp1414-100 0.5 mm plqp0100kb-a r5f562tabdff lqfp1414-80 0.65 mm plqp0080ja-a r5f562tabdfm lqfp1010-64 0.5 mm plqp0064kb-a r5f562t7bdfh lqfp2020-112 0.65 mm plqp0112ja-a 128 kbytes 8 kbytes 8k bytes r5f562t7bdfp lqfp1414-100 0.5 mm plqp0100kb-a r5f562t7bdff lqfp1414-80 0.65 mm plqp0080ja-a r5f562t7bdfm lqfp1010-6 4 0.5 mm plqp0064kb-a R5F562T6BDFF lqfp1414-80 0.65 mm plqp0080ja-a 64 kbytes 8 kbytes r5f562t6bdfm lqfp1010-6 4 0.5 mm plqp0064kb-a r5f562taddfh lqfp2020-112 0.65 mm plqp0112ja-a 256 kbytes 16 kbytes 32k bytes 4.0 to 5.5 v 4.0 to 5.5 v not supp orted r5f562taddfp lqfp1414-100 0.5 mm plqp0100kb-a r5f562taddff lqfp1414-80 0.65 mm plqp0080ja-a r5f562taddfm lqfp1010-64 0.5 mm plqp0064kb-a r5f562t7ddfh lqfp2020-112 0.65 mm plqp0112ja-a 128 kbytes 8 kbytes 8k bytes r5f562t7ddfp lqfp1414-100 0.5 mm plqp0100kb-a r5f562t7ddff lqfp1414-80 0.65 mm plqp0080ja-a r5f562t7ddfm lqfp1010-64 0.5 mm plqp0064kb-a r5f562t6dfff lqfp1414-80 0.65 mm plqp0080ja-a 64 kbytes 8 kbytes r5f562t6ddfm lqfp1010-64 0.5 mm plqp0064kb-a r5f562taedfh lqfp2020-112 0.65 mm plqp0112ja-a 256 kbytes 16 kbytes 32k bytes 2.7 to 3.6 v 3.0 to 3.6 v or 4.0 to 5.5 v r5f562taedfp lqfp1414-100 0.5 mm plqp0100kb-a r5f562taedff lqfp1414-80 0.65 mm plqp0080ja-a r5f562taedfm lqfp1010-64 0.5 mm plqp0064kb-a r5f562t7edfh lqfp2020-112 0.65 mm plqp0112ja-a 128 kbytes 8 kbytes 8k bytes r5f562t7edfp lqfp1414-100 0.5 mm plqp0100kb-a r5f562t7edff lqfp1414-80 0.65 mm plqp0080ja-a r5f562t7edfm lqfp1010-6 4 0.5 mm plqp0064kb-a r5f562t6edff lqfp1414-80 0.65 mm plqp0080ja-a 64 kbytes 8 kbytes r5f562t6edfm lqfp1010-6 4 0.5 mm plqp0064kb-a
r01ds0096ej0100 rev.1.00 page 9 of 92 apr 20, 2011 rx62t group 1. overview figure 1.1 how to read the product part no. indicates the type of memory. f: flash memory version r 5 f 5 6 2 t a b d f h indicates the package type, numb er of pins, and pin pitch. fh: lqfp112-0.65 fp: lqfp100-0.50 ff: lqfp80-0.65 fm: lqfp64-0.50 indicates the rom capacity, ra m capacity, and data flash capaci ty. a: 256 kbytes/16 kbytes/32 kbytes 7: 128 kbytes/8 kbytes/8 kbytes 6: 64 kbytes/8 kbytes/8 kbytes indicates a group name. 2t: rx62t group indicates a renesas mcu. indicates a renesas semiconductor product. a: 5-v version, can ?? 1 channel b: 3-v version, can ?? 1 channel d: 5-v version, can not supported e: 3-v version, can not supported indicates a series name (rx600 series)
r01ds0096ej0100 rev.1.00 page 10 of 92 apr 20, 2011 rx62t group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram rom ram rx cpu dtc por internal peripheral buses 1 to 6 icu port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port a port b port d port e clock generation circuit internal main bus 2 operand bus instruction bus riic 10-bit a/d converter ? 12 channels rspi iwdt sci ? 3 channels mtu3 port g crc can (as an optional function) poe3 cmt ? 2 channels (unit 0) lin notes: 1. the installation of the 10-bit a/d converter and ports 1 to g is different depending on the package. 2. for details on the internal peripheral bus configuration, see section 12, buses in the user's manual: hardware. * 2 12-bit a/d converter ? 4 channels (unit 0) programmable gain amps ? 3 channels sample-and-hold circuits for the pin section ? 3 channels window comparator ? 3 channels wdt data flash lvd can: can module lin: lin module rspi: renesas serial peripheral interface lvd: voltage detection circuit icu: interrupt control unit wdt: watchdog timer iwdt: independent watchdog timer crc: crc (cyclic redundancy check) calculator [legend] por: power-on reset circuit dtc: data transfer controller mtu3: multi-function timer pulse unit 3 poe3: port output enable 3 gpt: general pwm timer cmt: compare match timer sci: serial communications interface riic: i 2 c bus interface gpt 12-bit a/d converter ? 4 channels (unit 1) programmable gain amps ? 3 channels sample-and-hold circuits for the pin section ? 3 channels window comparator ? 3 channels cmt ? 2 channels (unit 1) internal main bus 1 * 1 * 1
r01ds0096ej0100 rev.1.00 page 11 of 92 apr 20, 2011 rx62t group 1. overview 1.4 pin assignments figure 1.3 to figure 1.6 show the pins assignments. table 1.4 to table 1.7 show the list of pins and pin functions. figure 1.3 pin assignment of the 112-pin lqfp p62/an2 p63/an3 p64/an4 p65/an5 p20/adtrg0#-b/mtclkb-b/irq7 p21/adtrg1#-b/mtclka-b/irq6 p22/adtrg#/crx-b/lrx/miso-a p23/ctx-b/ltx/mosi-a p24/rspck-a p30/mtioc0b-b/mtclkd-a/ssl0-a p31/mtioc0a-b/mtclkc-a/ssl1-a p32/mtioc3c/mtclkb-a/ssl2-a p33/mtioc3a/mtclka-a/ssl3-a vss p70/irq5/poe0# vcc p71/mtioc3b/gtioc0a-a p72/mtioc4a/gtioc1a-a p73/mtioc4b/gtioc2a-a p74/mtioc3d/gtioc0b-a p75/mtioc4c/gtioc1b-a p76/mtioc4d/gtioc2b-a p80/mtic5w/rxd2-b p81/mtic5v/txd2-b p82/mtic5u/sck2-b pg0/irq0-c/trsync pg1/irq1-c/trdata0 pg2/irq2-b/trdata1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 avss 56 pg3/trdata2 vref 55 pg4/trdata3 avcc 54 pg5/trclk p61/an1 53 p90/mtioc7d p60/an0 52 p91/mtioc7c p55/an11 51 p92/mtioc6d p54/an10 50 p93/mtioc7b p53/an9 49 p94/mtioc7a p52/an8 48 p95/mtioc6b p51/an7 47 vss p50/an6 46 p96/irq4/poe4# p47/an103/cvrefh 45 vcc p46/an102 44 pa0/mtioc6c/ssl3-b p45/an101 43 pa1/mtioc6a/ssl2-b p44/an100 42 pa2/mtioc2b/ssl1-b avcc0 41 pa3/mtioc2a/ssl0-b vrefh0 40 pa4/adtrg0#-a/mtioc1b/rspck-b p43/an003/cvrefl 39 pa5/adtrg1#-a/mtioc1a/miso-b p42/an002 38 pb0/mtioc0d/mosi-b p41/an001 37 pb1/mtioc0c/rxd0/scl p40/an000 36 pb2/mtioc0b-a/txd0/sda vrefl0 35 pb3/mtioc0a-a/sck0 avss0 34 pllvss wdtovf# 33 pb4/gtetrg/irq3/poe8# p11/mtclkc-b/irq1-a 32 pllvcc p10/mtclkd-b/irq0-a 31 pb5/ctx-a/txd2-a trst# 30 pb6/crx-a/rxd2-a tms 29 pb7/sck2-a pe5/irq0-b emle vss mde vcl md1 md0 pe4/mtclkc-c/irq1-b/poe10#-b pe3/mtclkd-c/irq2-a/poe11# res# xtal vss extal vcc pe2/nmi/poe10#-a pe1/ssl3-c pe0/crx-c/ssl2-c pd7/gtioc0a-b/ctx-c/ssl1-c pd6/gtioc0b-b/ssl0-c pd5/gtioc1a-b/rxd1 pd4/gtioc1b-b/sck1 pd3/gtioc2a-b/txd1 pd2/gtioc2b-b/mosi-c pd1/gtioc3a/miso-c pd0/gtioc3b/rspck-c tdi tck tdo 112 110 111 102 103 104 90 91 92 89 86 87 88 18 14 85 27 98 99 100 28 26 rx62t group plqp0112ja-a (112-pin lqfp) (top view) 106 107 108 109 105 101 97 93 94 95 96 1 2 7 8 3 4 5 6 10 11 9 17 15 13 12 16 19 25 24 22 23 20 21
r01ds0096ej0100 rev.1.00 page 12 of 92 apr 20, 2011 rx62t group 1. overview figure 1.4 pin assignment of the 100-pin lqfp pa0/mtioc6c/ssl3-b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p62/an2 p63/an3 p64/an4 p65/an5 p20/adtrg0#-b/mtclkb-b/irq7 p21/adtrg1#-b/mtclka-b/irq6 p22/adtrg#/crx-b/lrx/miso-a p23/ctx-b/ltx/mosi-a p24/rspck-a p30/mtioc0b-b/mtclkd-a/ssl0-a p31/mtioc0a-b/mtclkc-a/ssl1-a p32/mtioc3c/mtclkb-a/ssl2-a p33/mtioc3a/mtclka-a/ssl3-a vss p70/irq5/poe0# vcc p71/mtioc3b/gtioc0a-a p72/mtioc4a/gtioc1a-a p73/mtioc4b/gtioc2a-a p74/mtioc3d/gtioc0b-a p75/mtioc4c/gtioc1b-a p76/mtioc4d/gtioc2b-a p80/mtic5w/rxd2-b p81/mtic5v/txd2-b p82/mtic5u/sck2-b avcc p90/mtioc7d vref p91/mtioc7c avss p92/mtioc6d p61/an1 p93/mtioc7b p60/an0 p94/mtioc7a p55/an11 p95/mtioc6b p54/an10 vss p53/an9 p96/irq4/poe4# p52/an8 vcc p51/an7 p50/an6 pa1/mtioc6a/ssl2-b p47/an103/cvrefh pa2/mtioc2b/ssl1-b p46/an102 pa3/mtioc2a/ssl0-b p45/an101 pa4/adtrg0#-a/mtioc1b/rspck-b p44/an100 pa5/adtrg1#-a/mtioc1a/miso-b avcc0 pb0/mtioc0d/mosi-b vrefh0 pb1/mtioc0c/rxd0/scl p43/an003/cvrefl pb2/mtioc0b-a/txd0/sda p42/an002 pb3/mtioc0a-a/sck0 p41/an001 pllvss p40/an000 pb4/gtetrg/irq3/poe8# vrefl0 pllvcc avss0 pb5/ctx-a/txd2-a/trsync p11/mtclkc-b/irq1-a pb6/crx-a/rxd2-a/trdata0 p10/mtclkd-b/irq0-a pb7/sck2-a/trdata1 pe5/irq0-b emle vss mde vcl md1 md0 pe4/mtclkc-c/irq1-b/poe10#-b pe3/mtclkd-c/irq2-a/poe11# res# xtal vss extal vcc pe2/nmi/poe10#-a pe1/ssl3-c pe0/crx-c/ssl2-c pd7/gtioc0a-b/ctx-c/ssl1-c/trst# pd6/gtioc0b-b/ssl0-c/tms pd5/gtioc1a-b/rxd1/tdi pd4/gtioc1b-b/sck1/tck pd3/gtioc2a-b/txd1/tdo pd2/gtioc2b-b/mosi-c/trclk pd1/gtioc3a/miso-c/trdata3 pd0/gtioc3b/rspck-c/trdata2 rx62t group plqp0100kb-a (100-pin lqfp) (top view)
r01ds0096ej0100 rev.1.00 page 13 of 92 apr 20, 2011 rx62t group 1. overview figure 1.5 pin assignment of the 80-pin lqfp p62/an2 p63/an3 p20/adtrg0#-b/mtclkb-b/irq7 p21/adtrg1#-b/mtclka-b/irq6 p22/adtrg#/crx-b/lrx/miso-a p23/ctx-b/ltx/mosi-a p24/rspck-a p30/mtioc0b-b/mtclkd-a/ssl0-a p31/mtioc0a-b/mtclkc-a/ssl1-a vss p32/mtioc3c/mtclkb-a/ssl2-a vcc p33/mtioc3a/mtclka-a/ssl3-a p70/irq5/poe0# p71/mtioc3b/gtioc0a-a p72/mtioc4a/gtioc1a-a p73/mtioc4b/gtioc2a-a p74/mtioc3d/gtioc0b-a p75/mtioc4c/gtioc1b-a p76/mtioc4d/gtioc2b-a 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 avss 40 p91/mtioc7c avcc 39 p92/mtioc6d p61/an1 38 p93/mtioc7b p60/an0 37 p94/mtioc7a p47/an103/cvrefh 36 p95/mtioc6b p46/an102 35 vss p45/an101 34 p96/irq4/poe4# p44/an100 33 vcc avcc0 32 pa2/mtioc2b/ssl1-b vrefh0 31 pa3/mtioc2a/ssl0-b p43/an003/cvrefl 30 pb0/mtioc0d/mosi-b p42/an002 29 pb1/mtioc0c/rxd0/scl p41/an001 28 pb2/mtioc0b-a/txd0/sda p40/an000 27 pb3/mtioc0a-a/sck0 vrefl0 26 pllvss avss0 25 pb4/gtetrg/irq3/poe8# p11/mtclkc-b/irq1-a 24 pllvcc p10/mtclkd-b/irq0-a 23 pb5/ctx-a/txd2-a pa5/adtrg1#-a/mtioc1a/miso-b 22 pb6/crx-a/rxd2-a pa4/adtrg0#-a/mtioc1b/rspck-b 21 pb7/sck2-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 emle vss mde vcl md1 md0 pe4/mtclkc-c/irq1-b/poe10#-b pe3/mtclkd-c/irq2-a/poe11# res# xtal vss extal vcc pe2/nmi/poe10#-a pe0/crx-c pd7/gtioc0a-b/ctx-c/trst# pd6/gtioc0b-b/tms pd5/gtioc1a-b/rxd1/tdi pd4/gtioc1b-b/sck1/tck pd3/gtioc2a-b/txd1/tdo 77 73 74 75 76 68 69 80 78 79 72 63 70 71 67 65 66 62 61 64 rx62t group plqp0080ja-a (80-pin lqfp) (top view)
r01ds0096ej0100 rev.1.00 page 14 of 92 apr 20, 2011 rx62t group 1. overview figure 1.6 pin assignment of the 64-pin lqfp p22/crx-b/lrx/miso-a p23/ctx-b/ltx/mosi-a p24/rspck-a p30/mtioc0b-b/mtclkd-a/ssl0-a p31/mtioc0a-b/mtclkc-a/ssl1-a p32/mtioc3c/mtclkb-a/ssl2-a p33/mtioc3a/mtclka-a/ssl3-a vss p70/irq5/poe0# vcc p71/mtioc3b/gtioc0a-a p72/mtioc4a/gtioc1a-a p73/mtioc4b/gtioc2a-a p74/mtioc3d/gtioc0b-a p75/mtioc4c/gtioc1b-a p76/mtioc4d/gtioc2b-a 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p47/an103/cvrefh 32 p91/mtioc7c p46/an102 31 p92/mtioc6d p45/an101 30 p93/mtioc7b p44/an100 29 p94/mtioc7a avcc0 28 pa2/mtioc2b/ssl1-b vrefh0 27 pa3/mtioc2a/ssl0-b p43/an003/cvrefl 26 pb0/mtioc0d/mosi-b p42/an002 25 pb1/mtioc0c/rxd0/scl p41/an001 24 pb2/mtioc0b-a/txd0/sda p40/an000 23 pb3/mtioc0a-a/sck0 vrefl0 22 pb4/gtetrg/irq3/poe8# avss0 21 pb5/ctx-a/txd2-a p11/mtclkc-b/irq1-a 20 pllvss p10/mtclkd-b/irq0-a 19 pb6/crx-a/rxd2-a pa5/adtrg1#-a/mtioc1a/miso-b 18 pllvcc pa4/adtrg0#-a/mtioc1b/rspck-b 17 pb7/sck2-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 emle mde vcl md1 md0 res# xtal vss extal vcc pe2/nmi/poe10#-a pd7/gtioc0a-b/trst# pd6/gtioc0b-b/tms pd5/gtioc1a-b/rxd1/tdi pd4/gtioc1b-b/sck1/tck pd3/gtioc2a-b/txd1/tdo 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx62t group plqp0064kb-a (64-pin lqfp) (top view)
r01ds0096ej0100 rev.1.00 page 15 of 92 apr 20, 2011 rx62t group 1. overview table 1.4 list of pins and pin functions (112-pin lqfp) (1 / 3) pin no. (112-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging 1 pe5 irq0-b 2 emle 3 vss 4 mde 5 vcl 6 md1 7 md0 8 pe4 mtclkc-c irq1-b poe10#-b 9 pe3 mtclkd-c irq2-a poe11# 10 res# 11 xtal 12 vss 13 extal 14 vcc 15 pe2 nmi poe10#-a 16 pe1 ssl3-c 17 pe0 crx-c/ ssl2-c 18 pd7 gtioc0a-b ctx-c/ ssl1-c 19 pd6 gtioc0b-b ssl0-c 20 pd5 gtioc1a-b rxd1 21 pd4 gtioc1b-b sck1 22 pd3 gtioc2a-b txd1 23 pd2 gtioc2b-b mosi-c 24 pd1 gtioc3a miso-c 25 pd0 gtioc3b rspck-c 26 tdi 27 tck 28 tdo 29 pb7 sck2-a 30 pb6 crx-a/ rxd2-a 31 pb5 ctx-a/ txd2-a 32 pllvcc 33 pb4 gtetrg irq3 poe8# 34 pllvss 35 pb3 mtioc0a-a sck0 36 pb2 mtioc0b-a txd0/sda 37 pb1 mtioc0c rxd0/scl 38 pb0 mtioc0d mosi-b 39 pa5 adtrg1#-a mtioc1a miso-b 40 pa4 adtrg0#-a mtioc1b rspck-b 41 pa3 mtioc2a ssl0-b 42 pa2 mtioc2b ssl1-b 43 pa1 mtioc6a ssl2-b
r01ds0096ej0100 rev.1.00 page 16 of 92 apr 20, 2011 rx62t group 1. overview 44 pa0 mtioc6c ssl3-b 45 vcc 46 p96 irq4 poe4# 47 vss 48 p95 mtioc6b 49 p94 mtioc7a 50 p93 mtioc7b 51 p92 mtioc6d 52 p91 mtioc7c 53 p90 mtioc7d 54 pg5 trclk 55 pg4 trdata3 56 pg3 trdata2 57 pg2 irq2-b trdata1 58 pg1 irq1-c trdata0 59 pg0 irq0-c trsync 60 p76 mtioc4d/ gtioc2b-a 61 p75 mtioc4c/ gtioc1b-a 62 p74 mtioc3d/ gtioc0b-a 63 p73 mtioc4b/ gtioc2a-a 64 p72 mtioc4a/ gtioc1a-a 65 p71 mtioc3b/ gtioc0a-a 66 p70 irq5 poe0# 67 p33 mtioc3a/ mtclka-a ssl3-a 68 p32 mtioc3c/ mtclkb-a ssl2-a 69 vcc 70 p31 mtioc0a-b/ mtclkc-a ssl1-a 71 vss 72 p30 mtioc0b-b/ mtclkd-a ssl0-a 73 p24 rspck-a 74 p23 ctx-b/ ltx/ mosi-a 75 p22 adtrg# crx-b/ lrx/ miso-a 76 p21 adtrg1#-b mtclka-b irq6 77 p20 adtrg0#-b mtclkb-b irq7 78 p65 an5 79 p64 an4 table 1.4 list of pins and pin functions (112-pin lqfp) (2 / 3) pin no. (112-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging
r01ds0096ej0100 rev.1.00 page 17 of 92 apr 20, 2011 rx62t group 1. overview 80 avcc 81 vref 82 avss 83 p63 an3 84 p62 an2 85 p61 an1 86 p60 an0 87 p55 an11 88 p54 an10 89 p53 an9 90 p52 an8 91 p51 an7 92 p50 an6 93 p47 an103/ cvrefh 94 p46 an102 95 p45 an101 96 p44 an100 97 p43 an003/ cvrefl 98 p42 an002 99 p41 an001 100 p40 an000 101 avcc0 102 vrefh0 103 vrefl0 104 avss0 105 p82 mtic5u sck2-b 106 p81 mtic5v txd2-b 107 p80 mtic5w rxd2-b 108 wdtovf# 109 p11 mtclkc-b irq1-a 110 p10 mtclkd-b irq0-a 111 trst# 112 tms table 1.4 list of pins and pin functions (112-pin lqfp) (3 / 3) pin no. (112-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging
r01ds0096ej0100 rev.1.00 page 18 of 92 apr 20, 2011 rx62t group 1. overview table 1.5 list of pins and pin functions (100-pin lqfp) (1 / 3) pin no. (80-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging 1 pe5 irq0-b 2 emle 3 vss 4 mde 5 vcl 6 md1 7 md0 8 pe4 mtclkc-c irq1-b poe10#-b 9 pe3 mtclkd-c irq2-a poe11# 10 res# 11 xtal 12 vss 13 extal 14 vcc 15 pe2 nmi poe10#-a 16 pe1 ssl3-c 17 pe0 crx-c/ ssl2- c 18 pd7 gtioc0a-b ctx-c/ ssl1-c trst# 19 pd6 gtioc0b-b ssl0-c tms 20 pd5 gtioc1a-b rxd1 tdi 21 pd4 gtioc1b-b sck1 tck 22 pd3 gtioc2a-b txd1 tdo 23 pd2 gtioc2b-b mosi-c trclk 24 pd1 gtioc3a miso-c trdata3 25 pd0 gtioc3b rspck-c trdata2 26 pb7 sck2-a trdata1 27 pb6 crx-a/ rxd2- a trdata0 28 pb5 ctx-a/ txd2-a trsync 29 pllvcc 30 pb4 gtetrg irq3 poe8# 31 pllvss 32 pb3 mtioc0a-a sck0 33 pb2 mtioc0b-a txd0/sda 34 pb1 mtioc0c rxd0/scl 35 pb0 mtioc0d mosi-b 36 pa5 adtrg1#-a mtioc1a miso-b 37 pa4 adtrg0#-a mtioc1b rspck-b 38 pa3 mtioc2a ssl0-b 39 pa2 mtioc2b ssl1-b 40 pa1 mtioc6a ssl2-b
r01ds0096ej0100 rev.1.00 page 19 of 92 apr 20, 2011 rx62t group 1. overview 41 pa0 mtioc6c ssl3-b 42 vcc 43 p96 irq4 poe4# 44 vss 45 p95 mtioc6b 46 p94 mtioc7a 47 p93 mtioc7b 48 p92 mtioc6d 49 p91 mtioc7c 50 p90 mtioc7d 51 p76 mtioc4d/ gtioc2b-a 52 p75 mtioc4c/ gtioc1b-a 53 p74 mtioc3d/ gtioc0b-a 54 p73 mtioc4b/ gtioc2a-a 55 p72 mtioc4a/ gtioc1a-a 56 p71 mtioc3b/ gtioc0a-a 57 p70 irq5 poe0# 58 p33 mtioc3a/ mtclka-a ssl3-a 59 p32 mtioc3c/ mtclkb-a ssl2-a 60 vcc 61 p31 mtioc0a-b/ mtclkc-a ssl1-a 62 vss 63 p30 mtioc0b-b/ mtclkd-a ssl0-a 64 p24 rspck-a 65 p23 ctx-b/ ltx/ mosi-a 66 p22 adtrg# crx-b/ lrx/ miso-a 67 p21 adtrg1#-b mtclka-b irq6 68 p20 adtrg0#-b mtclkb-b irq7 69 p65 an5 70 p64 an4 71 avcc 72 vref 73 avss 74 p63 an3 75 p62 an2 76 p61 an1 table 1.5 list of pins and pin functions (100-pin lqfp) (2 / 3) pin no. (80-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging
r01ds0096ej0100 rev.1.00 page 20 of 92 apr 20, 2011 rx62t group 1. overview 77 p60 an0 78 p55 an11 79 p54 an10 80 p53 an9 81 p52 an8 82 p51 an7 83 p50 an6 84 p47 an103/ cvrefh 85 p46 an102 86 p45 an101 87 p44 an100 88 p43 an003/ cvrefl 89 p42 an002 90 p41 an001 91 p40 an000 92 avcc0 93 vrefh0 94 vrefl0 95 avss0 96 p82 mtic5u sck2-b 97 p81 mtic5v txd2-b 98 p80 mtic5w rxd2-b 99 p11 mtclkc-b irq1-a 100 p10 mtclkd-b irq0-a table 1.5 list of pins and pin functions (100-pin lqfp) (3 / 3) pin no. (80-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging
r01ds0096ej0100 rev.1.00 page 21 of 92 apr 20, 2011 rx62t group 1. overview table 1.6 list of pins and pin functions (80-pin lqfp) (1 / 3) pin no. (80-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging 1 emle 2 vss 3 mde 4 vcl 5 md1 6 md0 7 pe4 mtclkc-c irq1-b poe10#-b 8 pe3 mtclkd-c irq2-a poe11# 9 res# 10 xtal 11 vss 12 extal 13 vcc 14 pe2 nmi poe10#-a 15 pe0 crx-c 16 pd7 gtioc0a-b ctx-c trst# 17 pd6 gtioc0b-b tms 18 pd5 gtioc1a-b rxd1 tdi 19 pd4 gtioc1b-b sck1 tck 20 pd3 gtioc2a-b txd1 tdo 21 pb7 sck2-a 22 pb6 crx-a/ rxd2-a 23 pb5 ctx-a/ txd2-a 24 pllvcc 25 pb4 gtetrg irq3 poe8# 26 pllvss 27 pb3 mtioc0a-a sck0 28 pb2 mtioc0b-a txd0/sda 29 pb1 mtioc0c rxd0/scl 30 pb0 mtioc0d mosi-b 31 pa3 mtioc2a ssl0-b 32 pa2 mtioc2b ssl1-b 33 vcc 34 p96 irq4 poe4# 35 vss 36 p95 mtioc6b 37 p94 mtioc7a 38 p93 mtioc7b 39 p92 mtioc6d 40 p91 mtioc7c 41 p76 mtioc4d/ gtioc2b-a
r01ds0096ej0100 rev.1.00 page 22 of 92 apr 20, 2011 rx62t group 1. overview 42 p75 mtioc4c/ gtioc1b-a 43 p74 mtioc3d/ gtioc0b-a 44 p73 mtioc4b/ gtioc2a-a 45 p72 mtioc4a/ gtioc1a-a 46 p71 mtioc3b/ gtioc0a-a 47 p70 irq5 poe0# 48 p33 mtioc3a/ mtclka-a ssl3-a 49 p32 mtioc3c/ mtclkb-a ssl2-a 50 vcc 51 p31 mtioc0a-b/ mtclkc-a ssl1-a 52 vss 53 p30 mtioc0b-b/ mtclkd-a ssl0-a 54 p24 rspck-a 55 p23 ctx-b/ ltx/ mosi-a 56 p22 adtrg# crx-b/ lrx/ miso-a 57 p21 adtrg1#-b mtclka-b irq6 58 p20 adtrg0#-b mtclkb-b irq7 59 avcc 60 avss 61 p63 an3 62 p62 an2 63 p61 an1 64 p60 an0 65 p47 an103/ cvrefh 66 p46 an102 67 p45 an101 68 p44 an100 69 p43 an003/ cvrefl 70 p42 an002 71 p41 an001 72 p40 an000 73 avcc0 74 vrefh0 75 vrefl0 table 1.6 list of pins and pin functions (80-pin lqfp) (2 / 3) pin no. (80-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging
r01ds0096ej0100 rev.1.00 page 23 of 92 apr 20, 2011 rx62t group 1. overview 76 avss0 77 p11 mtclkc-b irq1-a 78 p10 mtclkd-b irq0-a 79 pa5 adtrg1#-a mtioc1a miso-b 80 pa4 adtrg0#-a mtioc1b rspck-b table 1.6 list of pins and pin functions (80-pin lqfp) (3 / 3) pin no. (80-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debugging
r01ds0096ej0100 rev.1.00 page 24 of 92 apr 20, 2011 rx62t group 1. overview table 1.7 list of pins and pin functions (64-pin lqfp) (1 / 2) pin no. (64-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debuggi ng 1 emle 2 mde 3 vcl 4 md1 5 md0 6 res# 7 xtal 8 vss 9 extal 10 vcc 11 pe2 nmi poe10#-a 12 pd7 gtioc0a-b trst# 13 pd6 gtioc0b-b tms 14 pd5 gtioc1a-b rxd1 tdi 15 pd4 gtioc1b-b sck1 tck 16 pd3 gtioc2a-b txd1 tdo 17 pb7 sck2-a 18 pb6 crx-a/ rxd2-a 19 pb5 ctx-a/ txd2-a 20 pllvcc 21 pb4 gtetrg irq3 poe8# 22 pllvss 23 pb3 mtioc0a-a sck0 24 pb2 mtioc0b-a txd0/sda 25 pb1 mtioc0c rxd0/scl 26 pb0 mtioc0d mosi-b 27 pa3 mtioc2a ssl0-b 28 pa2 mtioc2b ssl1-b 29 p94 mtioc7a 30 p93 mtioc7b 31 p92 mtioc6d 32 p91 mtioc7c 33 p76 mtioc4d/ gtioc2b-a 34 p75 mtioc4c/ gtioc1b-a 35 p74 mtioc3d/ gtioc0b-a 36 p73 mtioc4b/ gtioc2a-a 37 p72 mtioc4a/ gtioc1a-a 38 p71 mtioc3b/ gtioc0a-a 39 p70 irq5 poe0#
r01ds0096ej0100 rev.1.00 page 25 of 92 apr 20, 2011 rx62t group 1. overview 40 p33 mtioc3a/ mtclka-a ssl3-a 41 p32 mtioc3c/ mtclkb-a ssl2-a 42 vcc 43 p31 mtioc0a-b/ mtclkc-a ssl1-a 44 vss 45 p30 mtioc0b-b/ mtclkd-a ssl0-a 46 p24 rspck-a 47 p23 ctx-b/ ltx/ mosi-a 48 p22 crx-b/ lrx/ miso-a 49 p47 an103/ cvrefh 50 p46 an102 51 p45 an101 52 p44 an100 53 p43 an003/ cvrefl 54 p42 an002 55 p41 an001 56 p40 an000 57 avcc0 58 vrefh0 59 vrefl0 60 avss0 61 p11 mtclkc-b irq1-a 62 p10 mtclkd-b irq0-a 63 pa5 adtrg1#-a mtioc1a miso-b 64 pa4 adtrg0#-a mtioc1b rspck-b table 1.7 list of pins and pin functions (64-pin lqfp) (2 / 2) pin no. (64-pin lqfp) power supply clock system control i/o port analog timer communi- cation interrupt poe debuggi ng
r01ds0096ej0100 rev.1.00 page 26 of 92 apr 20, 2011 rx62t group 1. overview 1.5 pin functions table 1.8 lists the pin functions. table 1.8 pin functions (1 / 4) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl input connect this pin to vss via a 0.1- ? f capacitor. the capacitor should be placed close to the pin. vss input ground pin. connect it to the system power supply (0 v). pllvcc input power supply pin for the pll circuit. connect it to the system power supply. pllvss input ground pin for the pll circuit. clock xtal output pins for a crystal resona tor. an external clock signal can be input through the extal pin. extal input operating mode control md0 md1 mde input pins for setting the operating mode. the signal levels on these pins must not be changed during operation. system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low. emle input input pin for the on-chip emulator enable signal. when the on- chip emulator is used, this pin should be driven high. when not used, it should be driven low. on-chip emulator trst# input on-chip emulator pins. when the emle pin is driven high, these pins are dedicated for the on-chip emulator. tms input tdi input tck input tdo output trclk output this pin outputs the clock for synchronization with the trace data. not included in the 80-/64-pin versions. trsync output this pin indicates that output from the trdata0 to trdata3 pins is valid. not included in the 80-/64-pin versions. trdata0 to trdata3 output these pins output the trace information. not included in the 80- /64-pin versions. interrupt (icu) nmi input non-maskable interrupt request signal. irq0-a/irq0-b/irq0-c irq1-a/irq1-b/irq1-c irq2-a/irq2-b irq3 to irq7 input interrupt request signals. the irq0-c/irq1-c/irq2-b pin is not included in the 100-pin version. the irq0-b/irq0-c/irq1-c/ irq2-b pin is not included in the 80-pin version. the irq0-b/ irq0-c/irq1-b/irq1-/irq2-a/irq2-b/irq4/irq6/irq7 pin is not included in the 64-pin version.
r01ds0096ej0100 rev.1.00 page 27 of 92 apr 20, 2011 rx62t group 1. overview multi-function timer pulse unit 3 (mtu3) mtioc0a-a/mtioc0a-b mtioc0b-a/mtioc0b-b mtioc0c, mtioc0d i/o the mtu0.tgra to mtu0.tgrd input capture input/output compare output/pwm output pins. mtioc1a, mtioc1b i/o the mtu1.tgra and mtu1.tgrb input capture input/output compare output/pwm output pins. mtioc2a, mtioc2b i/o the mtu2.tgra and mtu2.tgrb input capture input/output compare output/pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the mtu3.tgra and mtu3.tgrd input capture input/output compare output/pwm output pins. pins mtioc3b and mtioc3d can be used for large-current output. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the mtu4.tgra and mtu4.tgrd input capture input/output compare output/pwm output pins. these pins can be used for large-current output. mtic5u, mtic5v, mtic5w input the mtu5.t gru, mtu5.tgrv, and mtu5.tgrw input capture input/dead time compens ation input pins. not included in the 80-/64-pin versions. mtioc6a, mtioc6b mtioc6c, mtioc6d i/o the mtu6.tgra to mtu6.tgrd input capture input/output compare output/pwm output pins. pins mtioc6b and mtioc6d can be used for large-current output. the mtioc6a/mtioc6c pin is not included in the 80-pin version. the mtioc6a/mtioc6b/mt ioc6c pin is not included in the 64-pin version. mtioc7a, mtioc7b mtioc7c, mtioc7d i/o the mtu7.tgra to mtu7.tgrd input capture input/output compare output/pwm output pins. these pins can be used for large-current output. the mtioc7d pin is not included in the 80-/64-pin versions. mtclka-a/mtclka-b mtclkb-a/mtclkb-b mtclkc-a/mtclkc-b/ mtclkc-c mtclkd-a/mtclkd-b/ mtclkd-c input input pins for external clock signals. the mtclka-b/mtclkb-b/ mtclkc-c/mtclkd-c pin is not included in the 64-pin version. general pwm timer (gpt) gtioc0a-a/gtioc0a-b gtioc0b-a/gtioc0b-b i/o the gpt0.gtccra and gpt0.gtccrb ccrb input capture input/output compare output/pwm output pins. pins gtioc0a-a and gtioc0b-a can be used for large- current output. gtioc1a-a/gtioc1a-b gtioc1b-a/gtioc1b-b i/o the gpt1.gtccra and gpt1.gtccrb input capture input/ output compare output/pwm output pins. pins gtioc1a-a and gtioc1b-a can be used for large- current output. gtioc2a-a/gtioc2a-b gtioc2b-a/gtioc2b-b i/o the gpt2.gtccra and gpt2.gtccrb input capture input/ output compare output/pwm output pins. pins gtioc2a-a and gtioc2b-a can be used for large- current output. the gtioc2b-b pin is not included in the 80- pin version. gtioc3a, gtioc3b i/o the gpt3.gtccra and gpt3.gtccrb input capture input/ output compare output/pwm output pins. not included in the 80-/64-pin versions. gtetrg input external trigger input pin for the gpt port output enable 3 (poe3) poe0#, poe4#, poe8# poe10#-a/poe10#-b poe11# input input pins for request signals to place the mtu3 and gpt large-current pins in the high impedance state. the poe4#/ poe10#-b/poe11# pin is not in cluded in the 64-pin version. watchdog timer (wdt) wdtovf# output output pin fo r the counter-overflow signal in watchdog-timer mode. not included in the 100-/80-/64-pin versions. table 1.8 pin functions (2 / 4) classifications pin name i/o description
r01ds0096ej0100 rev.1.00 page 28 of 92 apr 20, 2011 rx62t group 1. overview serial communications interface (scib) txd0, txd1?txd2-a/txd2- b output output pins for data transmi ssion. the txd2-b pin is not included in the 80-/64-pin versions. rxd0, rxd1, rxd2-a/ rxd2-b input input pins for data reception. the rxd2-b pin is not included in the 80-/64-pin versions. sck0, sck1, sck2-a/ sck2-b i/o input/output pins for clock signals. the sck2-b pin is not included in the 80-/64-pin versions. i 2 c bus interface (riic) scl i/o input/output pin for i 2 c bus interface clocks . bus can be directly driven by the nmos open drain output. sda i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the nmos open drain output. can module (can) (as an optional function) crx-a/crx-b/crx-c input input pin for the can. the crx-c pin is not included in the 64- pin version. ctx-a/ctx-b/ctx-c output output pin for the can. the ctx-c pin is not included in the 64-pin version. lin module (lin) lrx input input pin for the lin. ltx output output pin for the lin. serial peripheral interface (rspi) rspck-a/rspck-b/ rspck-c i/o clock input/output pin for the rspi. the rspck-c pin is not included in the 80-/64-pin versions. mosi-a/mosi-b/mosi-c i/o inputs or outputs data output from the master for the rspi. the mosi-c pin is not included in the 80-/64-pin versions. miso-a/miso-b/miso-c i/o inputs or outputs data output from the slave for the rspi. the miso-c pin is not included in the 80-/64-pin versions. ssl0-a/ssl0-b/ssl0-c i/o select the slave for the rspi. the ssl0-c/ssl1-c/ssl2-c/ ssl3-c pin is not included in the 80-/64-pin versions. ssl1-a/ssl1-b/ssl1-c ssl2-a/ssl2-b/ssl2-c ssl3-a/ssl3-b/ssl3-c output a/d converter an000 to an003 an100 to an103 input input pins for the analog signals to be processed by the 12-bit a/d converter. an0 to an11 input input pins for the analog signals to be processed by the 10-bit a/d converter. the an4 to an11 pins are not included in the 80-pin version. not included in the 64-pin version. adtrg0#-a/adtrg0#-b adtrg1#-a/adtrg1#-b adtrg# input input pins for the external trigger signals that start the a/d conversion. the adtrg0#-b/ad trg1#-b/adtrg# pin is not included in the 64-pin version. cvrefh input input pin for the high-level reference voltage to the comparator cvrefl input input pin for the low-level reference voltage to the comparator analog power supply avcc0 input analog power supply pin for the 12-bit a/d converter. when the a/d converter is not in use, connect this pin to the system power supply. avss0 input ground pin for the 12-bit a/d converter. connect this pin to the system power supply (0 v). vrefh0 input reference power supply pin for the 12-bit a/d converter. when the 12-bit a/d converter is not in use, connect this pin to the system power supply. vrefl0 input ground pin of the reference power supply pin for the 12-bit a/d converter. when the 12-bit a/d converter is not in use, connect this pin to the system power supply (0 v). avcc input analog power supply pin for the 10-bit a/d converter. when the a/d converter is not in use, connect this pin to the system power supply. not included in the 64-pin version. avss input ground pin for the 10-bit a/d converter. connect this pin to the system power supply (0 v). not included in the 64-pin version. vref input reference power supply pin fo r the 10-bit a/d converter. when the 10-bit a/d converter is not in use, connect this pin to the system power supply. not included in the 80-/64-pin versions. table 1.8 pin functions (3 / 4) classifications pin name i/o description
r01ds0096ej0100 rev.1.00 page 29 of 92 apr 20, 2011 rx62t group 1. overview note: ? which pins are and are not incorporated depends on the package. for details, see the list of pins and pi n functions in table 1.4 to table 1.7. i/o ports p10, p11 i/o 2-bit input/output pins. p20 to p24 i/o 5-bit input/output pins. the p20/p21 pin is not included in the 64-pin version. p30 to p33 i/o 4-bit input/output pins. p40 to p47 input 8-bit input pins. p50 to p55 input 6-bit input pins. not included in the 80-/64-pin versions. p60 to p65 input 6-bit input pins. the p64/p6 pin is not included in the 80-pin version. not included in the 64-pin version. p70 to p76 i/o 7-bit input/output pins. p80 to p82 i/o 3-bit input/output pins. not included in the 80-/64-pin versions. p90 to p96 i/o 7-bit input/output pins. t he p90 pin is not included in the 80-pin version. the p90/p95/p96 pin is not included in the 64-pin version. pa0 to pa5 i/o 6-bit input/output pins. the pa0/pa1 pin is not included in the 80-/64-pin versions. pb0 to pb7 i/o 8-bit input/output pins. pd0 to pd7 i/o 8-bit input/output pins. th e pd0/pd1/pd2 pin is not included in the 80-/64-pin versions. pe0, pe1, pe3 to pe5 i/o 5-bit input/output pins. the pe1/pe5 pin is not included in the 80-pin version. not included in the 64-pin version. pe2 input 1-bit input pin. pg0 to pg5 i/o 6-bit input/output pins . not included in the 100-/80-/64-pin versions. table 1.8 pin functions (4 / 4) classifications pin name i/o description
r01ds0096ej0100 rev.1.00 page 30 of 92 apr 20, 2011 rx62t group 2. cpu 2. cpu the rx cpu has sixteen general-purpose registers, nine control registers, and one accumulator used for dsp instructions. figure 2.1 register set of the cpu note: * the stack pointer (sp) can be the interrupt st ack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw register. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) fpsw (floating-point status word) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) * general-purpose register control register b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator)
r01ds0096ej0100 rev.1.00 page 31 of 92 apr 20, 2011 rx62t group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen general-purpose registers (r0 to r15). r1 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by th e value of the stack pointer se lect bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (i sp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of four, as this reduces th e numbers of cycles required to execute interrupt sequences and instructions entai ling stack manipulation. (2) interrupt table register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. set intb to a multiple of four. (3) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (4) processor status word (psw) the processor status word (psw) indicates results of instruction execution or the state of the cpu. (5) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the conten ts of the program counter (pc) are saved in the bpc. (6) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. (8) floating-point status word (fpsw) the floating-point status word (fpsw) indicates the results of floating-point operations. when an exception handling enable bit (e j) enables the exception handling (ej = 1) , the exception cause can be identified by checking the corresponding cj flag in the exception handling routine. if th e exception handling is masked (ej = 0), the occurrence of exception can be ch ecked by reading the fj flag at the end of a series of pro cessing. once the fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = x, u, z, o, or v).
r01ds0096ej0100 rev.1.00 page 32 of 92 apr 20, 2011 rx62t group 2. cpu (9) accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instru ctions. the accumulator is also used for the multiply and multiply-and-accumulate instructions; em ul, emulu, fmul, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
r01ds0096ej0100 rev.1.00 page 33 of 92 apr 20, 2011 rx62t group 3. address space 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps. figure 3.1 memory map (rx62t group) reserved area* 2 reserved area* 2 0000 0000h 0008 0000h ffff ffffh single-chip mode * 1 on-chip ram reserved area* 2 on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 8000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) fffc 0000h fcu-ram* 3 reserved area* 2 peripheral i/o registers reserved area* 2 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0000 4000h reserved area* 2 00fc 0000h on-chip rom (fcu firmware)* 3 (read only) reserved area* 2 feff e000h ff00 0000h r5f562taxxxx reserved area* 2 reserved area* 2 0000 0000h 0008 0000h ffff ffffh single-chip mode * 1 on-chip ram reserved area* 2 on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 2000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) fffe 0000h fcu-ram* 3 reserved area* 2 peripheral i/o registers reserved area* 2 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0000 2000h reserved area* 2 00fe 0000h on-chip rom (fcu firmware)* 3 (read only) reserved area* 2 feff e000h ff00 0000h r5f562t7xxxx reserved area* 2 reserved area* 2 0000 0000h 0008 0000h ffff ffffh single-chip mode * 1 on-chip ram reserved area* 2 on-chip rom (program rom) (read only) 0010 0000h peripheral i/o registers 0010 2000h on-chip rom (data flash) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) ffff 0000h fcu-ram* 3 reserved area* 2 peripheral i/o registers reserved area* 2 peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0000 2000h reserved area* 2 00ff 0000h on-chip rom (fcu firmware)* 3 (read only) reserved area* 2 feff e000h ff00 0000h r5f562t6xxxx notes: 1. the layout of the address space in boot mode is the same as in single-chip mode. 2. reserved areas should not be accessed, since the correct operation of lsi is not guaranteed if they are accessed. 3. for details on the fcu, see section 30, rom (flash memory for code storage) and section 31, data flash (flash memory for data storage) in the user?s manual: hardware.
r01ds0096ej0100 rev.1.00 page 34 of 92 apr 20, 2011 rx62t group 4. i/o registers 4. i/o registers table 4.1 list of i/o register s (address order) (1 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles 0008 0000h system mode monitor register mdmonr 16 16 3iclk 0008 0002h system mode status register mdsr 16 16 3iclk 0008 0006h system system control register 0 syscr0 16 16 3iclk 0008 0008h system system control register 1 syscr1 16 16 3iclk 0008 000ch system standby control register sbycr 16 16 3iclk 0008 0010h system module stop control register a mstpcra 32 32 3iclk 0008 0014h system module stop control register b mstpcrb 32 32 3iclk 0008 0018h system module stop control register c mstpcrc 32 32 3iclk 0008 0020h system system clock control register sckcr 32 32 3iclk 0008 0040h system oscillation stop detection control register ostdcr 16 16 3iclk 0008 1300h bsc bus error status clear register berclr 8 8 2iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2iclk 0008 2400h dtc dtc control register dtccr 8 8 2iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2iclk 0008 240ch dtc dtc module start register dtcst 8 8 2iclk 0008 240eh dtc dtc status register dtcsts 16 16 2iclk 0008 7010h icu interrupt request register 016 ir016 8 8 2iclk 0008 7015h icu interrupt request register 021 ir021 8 8 2iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2iclk 0008 7038h icu interrupt request register 056 ir056 8 8 2iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2iclk 0008 703ah icu interrupt request register 058 ir058 8 8 2iclk 0008 703bh icu interrupt request register 059 ir059 8 8 2iclk 0008 703ch icu interrupt request register 060 ir060 8 8 2iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2iclk
r01ds0096ej0100 rev.1.00 page 35 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 7046h icu interrupt request register 070 ir070 8 8 2iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2iclk 0008 7060h icu interrupt request register 096 ir096 8 8 2iclk 0008 7062h icu interrupt request register 098 ir098 8 8 2iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2iclk 0008 708eh icu interrupt request register 142 ir142 8 8 2iclk 0008 708fh icu interrupt request register 143 ir143 8 8 2iclk 0008 7090h icu interrupt request register 144 ir144 8 8 2iclk 0008 7091h icu interrupt request register 145 ir145 8 8 2iclk 0008 7092h icu interrupt request register 146 ir146 8 8 2iclk 0008 7095h icu interrupt request register 149 ir149 8 8 2iclk 0008 7096h icu interrupt request register 150 ir150 8 8 2iclk 0008 7097h icu interrupt request register 151 ir151 8 8 2iclk 0008 7098h icu interrupt request register 152 ir152 8 8 2iclk table 4.1 list of i/o register s (address order) (2 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 36 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 7099h icu interrupt request register 153 ir153 8 8 2iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2iclk 0008 70ach icu interrupt request register 172 ir172 8 8 2iclk 0008 70adh icu interrupt request register 173 ir173 8 8 2iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2iclk 0008 70bah icu interrupt request register 186 ir186 8 8 2iclk 0008 70bbh icu interrupt request register 187 ir187 8 8 2iclk 0008 70bch icu interrupt request register 188 ir188 8 8 2iclk 0008 70bdh icu interrupt request register 189 ir189 8 8 2iclk 0008 70beh icu interrupt request register 190 ir190 8 8 2iclk 0008 70c0h icu interrupt request register 192 ir192 8 8 2iclk 0008 70c1h icu interrupt request register 193 ir193 8 8 2iclk 0008 70c2h icu interrupt request register 194 ir194 8 8 2iclk 0008 70c3h icu interrupt request register 195 ir195 8 8 2iclk 0008 70c4h icu interrupt request register 196 ir196 8 8 2iclk 0008 70d6h icu interrupt request register 214 ir214 8 8 2iclk 0008 70d7h icu interrupt request register 215 ir215 8 8 2iclk 0008 70d8h icu interrupt request register 216 ir216 8 8 2iclk 0008 70d9h icu interrupt request register 217 ir217 8 8 2iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2iclk 0008 70feh icu interrupt request register 254 ir254 8 8 2iclk 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2iclk table 4.1 list of i/o register s (address order) (3 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 37 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2iclk 0008 712dh icu dtc activation enable register 045 dtcer045 8 8 2iclk 0008 712eh icu dtc activation enable register 046 dtcer046 8 8 2iclk 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2iclk 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2iclk 0008 7146h icu dtc activation enable register 070 dtcer070 8 8 2iclk 0008 7147h icu dtc activation enable register 071 dtcer071 8 8 2iclk 0008 7162h icu dtc activation enable register 098 dtcer098 8 8 2iclk 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2iclk 0008 7167h icu dtc activation enable register 103 dtcer103 8 8 2iclk 0008 716ah icu dtc activation enable register 106 dtcer106 8 8 2iclk 0008 7172h icu dtc activation enable register 114 dtcer114 8 8 2iclk 0008 7173h icu dtc activation enable register 115 dtcer115 8 8 2iclk 0008 7174h icu dtc activation enable register 116 dtcer116 8 8 2iclk 0008 7175h icu dtc activation enable register 117 dtcer117 8 8 2iclk 0008 7179h icu dtc activation enable register 121 dtcer121 8 8 2iclk 0008 717ah icu dtc activation enable register 122 dtcer122 8 8 2iclk 0008 717dh icu dtc activation enable register 125 dtcer125 8 8 2iclk 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2iclk 0008 7182h icu dtc activation enable register 130 dtcer130 8 8 2iclk 0008 7183h icu dtc activation enable register 131 dtcer131 8 8 2iclk 0008 7184h icu dtc activation enable register 132 dtcer132 8 8 2iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2iclk 0008 7187h icu dtc activation enable register 135 dtcer135 8 8 2iclk 0008 7188h icu dtc activation enable register 136 dtcer136 8 8 2iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2iclk 0008 718bh icu dtc activation enable register 139 dtcer139 8 8 2iclk 0008 718ch icu dtc activation enable register 140 dtcer140 8 8 2iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2iclk 0008 718eh icu dtc activation enable register 142 dtcer142 8 8 2iclk 0008 718fh icu dtc activation enable register 143 dtcer143 8 8 2iclk 0008 7190h icu dtc activation enable register 144 dtcer144 8 8 2iclk 0008 7191h icu dtc activation enable register 145 dtcer145 8 8 2iclk 0008 7195h icu dtc activation enable register 149 dtcer149 8 8 2iclk 0008 7196h icu dtc activation enable register 150 dtcer150 8 8 2iclk table 4.1 list of i/o register s (address order) (4 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 38 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 7197h icu dtc activation enable register 151 dtcer151 8 8 2iclk 0008 7198h icu dtc activation enable register 152 dtcer152 8 8 2iclk 0008 7199h icu dtc activation enable register 153 dtcer153 8 8 2iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2iclk 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2iclk 0008 71b0h icu dtc activation enable register 176 dtcer176 8 8 2iclk 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2iclk 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2iclk 0008 71b3h icu dtc activation enable register 179 dtcer179 8 8 2iclk 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2iclk 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2iclk 0008 71b6h icu dtc activation enable register 182 dtcer182 8 8 2iclk 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2iclk 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2iclk 0008 71bah icu dtc activation enable register 186 dtcer186 8 8 2iclk 0008 71bbh icu dtc activation enable register 187 dtcer187 8 8 2iclk 0008 71bch icu dtc activation enable register 188 dtcer188 8 8 2iclk 0008 71bdh icu dtc activation enable register 189 dtcer189 8 8 2iclk 0008 71beh icu dtc activation enable register 190 dtcer190 8 8 2iclk 0008 71c0h icu dtc activation enable register 192 dtcer192 8 8 2iclk 0008 71c1h icu dtc activation enable register 193 dtcer193 8 8 2iclk 0008 71c2h icu dtc activation enable register 194 dtcer194 8 8 2iclk 0008 71c3h icu dtc activation enable register 195 dtcer195 8 8 2iclk 0008 71c4h icu dtc activation enable register 196 dtcer196 8 8 2iclk 0008 71d7h icu dtc activation enable register 215 dtcer215 8 8 2iclk 0008 71d8h icu dtc activation enable register 216 dtcer216 8 8 2iclk 0008 71dbh icu dtc activation enable register 219 dtcer219 8 8 2iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2iclk 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2iclk 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2iclk 0008 71feh icu dtc activation enable register 254 dtcer254 8 8 2iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2iclk 0008 7207h icu interrupt request enable register 07 ier07 8 8 2iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2iclk table 4.1 list of i/o register s (address order) (5 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 39 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 7212h icu interrupt request enable register 12 ier12 8 8 2iclk 0008 7213h icu interrupt request enable register 13 ier13 8 8 2iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2iclk 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2iclk 0008 72f0h icu fast interrupt set register fir 16 16 2iclk 0008 7300h icu interrupt source priority register 00 ipr00 8 8 2iclk 0008 7301h icu interrupt source priority register 01 ipr01 8 8 2iclk 0008 7302h icu interrupt source priority register 02 ipr02 8 8 2iclk 0008 7303h icu interrupt source priority register 03 ipr03 8 8 2iclk 0008 7304h icu interrupt source priority register 04 ipr04 8 8 2iclk 0008 7305h icu interrupt source priority register 05 ipr05 8 8 2iclk 0008 7306h icu interrupt source priority register 06 ipr06 8 8 2iclk 0008 7307h icu interrupt source priority register 07 ipr07 8 8 2iclk 0008 7314h icu interrupt source priority register 14 ipr14 8 8 2iclk 0008 7318h icu interrupt source priority register 18 ipr18 8 8 2iclk 0008 7320h icu interrupt source priority register 20 ipr20 8 8 2iclk 0008 7321h icu interrupt source priority register 21 ipr21 8 8 2iclk 0008 7322h icu interrupt source priority register 22 ipr22 8 8 2iclk 0008 7323h icu interrupt source priority register 23 ipr23 8 8 2iclk 0008 7324h icu interrupt source priority register 24 ipr24 8 8 2iclk 0008 7325h icu interrupt source priority register 25 ipr25 8 8 2iclk 0008 7326h icu interrupt source priority register 26 ipr26 8 8 2iclk 0008 7327h icu interrupt source priority register 27 ipr27 8 8 2iclk 0008 7340h icu interrupt source priority register 40 ipr40 8 8 2iclk 0008 7344h icu interrupt source priority register 44 ipr44 8 8 2iclk 0008 7348h icu interrupt source priority register 48 ipr48 8 8 2iclk 0008 7349h icu interrupt source priority register 49 ipr49 8 8 2iclk 0008 7351h icu interrupt source priority register 51 ipr51 8 8 2iclk 0008 7352h icu interrupt source priority register 52 ipr52 8 8 2iclk 0008 7353h icu interrupt source priority register 53 ipr53 8 8 2iclk 0008 7354h icu interrupt source priority register 54 ipr54 8 8 2iclk 0008 7355h icu interrupt source priority register 55 ipr55 8 8 2iclk 0008 7356h icu interrupt source priority register 56 ipr56 8 8 2iclk 0008 7357h icu interrupt source priority register 57 ipr57 8 8 2iclk 0008 7358h icu interrupt source priority register 58 ipr58 8 8 2iclk 0008 7359h icu interrupt source priority register 59 ipr59 8 8 2iclk table 4.1 list of i/o register s (address order) (6 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 40 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 735ah icu interrupt source priority register 5a ipr5a 8 8 2iclk 0008 735bh icu interrupt source priority register 5b ipr5b 8 8 2iclk 0008 735ch icu interrupt source priority register 5c ipr5c 8 8 2iclk 0008 735dh icu interrupt source priority register 5d ipr5d 8 8 2iclk 0008 735eh icu interrupt source priority register 5e ipr5e 8 8 2iclk 0008 735fh icu interrupt source priority register 5f ipr5f 8 8 2iclk 0008 7360h icu interrupt source priority register 60 ipr60 8 8 2iclk 0008 7367h icu interrupt source priority register 67 ipr67 8 8 2iclk 0008 7368h icu interrupt source priority register 68 ipr68 8 8 2iclk 0008 7369h icu interrupt source priority register 69 ipr69 8 8 2iclk 0008 736ah icu interrupt source priority register 6a ipr6a 8 8 2iclk 0008 736bh icu interrupt source priority register 6b ipr6b 8 8 2iclk 0008 736ch icu interrupt source priority register 6c ipr6c 8 8 2iclk 0008 736dh icu interrupt source priority register 6d ipr6d 8 8 2iclk 0008 736eh icu interrupt source priority register 6e ipr6e 8 8 2iclk 0008 736fh icu interrupt source priority register 6f ipr6f 8 8 2iclk 0008 7380h icu interrupt source priority register 80 ipr80 8 8 2iclk 0008 7381h icu interrupt source priority register 81 ipr81 8 8 2iclk 0008 7382h icu interrupt source priority register 82 ipr82 8 8 2iclk 0008 7388h icu interrupt source priority register 88 ipr88 8 8 2iclk 0008 7389h icu interrupt source priority register 89 ipr89 8 8 2iclk 0008 738ah icu interrupt source priority register 8a ipr8a 8 8 2iclk 0008 738bh icu interrupt source priority register 8b ipr8b 8 8 2iclk 0008 7390h icu interrupt source priority register 90 ipr90 8 8 2iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2iclk 0008 7582h icu non-maskable interrupt clear register nmiclr 8 8 2iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2 to 3pclk *5 0008 8002h cmt0 compare match timer control register cmcr 16 16 2 to 3pclk *5 0008 8004h cmt0 compare match timer counter cmcnt 16 16 2 to 3pclk *5 0008 8006h cmt0 compare match timer constant register cmcor 16 16 2 to 3pclk *5 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 to 3pclk *5 0008 800ah cmt1 compare match timer counter cmcnt 16 16 2 to 3pclk *5 0008 800ch cmt1 compare match timer constant register cmcor 16 16 2 to 3pclk *5 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2 to 3pclk *5 table 4.1 list of i/o register s (address order) (7 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 41 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 8012h cmt2 compare match timer control register cmcr 16 16 2 to 3pclk *5 0008 8014h cmt2 compare match timer counter cmcnt 16 16 2 to 3pclk *5 0008 8016h cmt2 compare match timer constant register cmcor 16 16 2 to 3pclk *5 0008 8018h cmt3 compare match timer control register cmcr 16 16 2 to 3pclk *5 0008 801ah cmt3 compare match timer counter cmcnt 16 16 2 to 3pclk *5 0008 801ch cmt3 compare match timer constant register cmcor 16 16 2 to 3pclk *5 0008 8028h wdt timer control/status register tcsr 8 8 2 to 3pclk *5 0008 8028h wdt write window a register wina 16 16 2 to 3pclk *5 0008 8029h wdt timer counter tcnt 8 8 2 to 3pclk *5 0008 802ah wdt write window b register winb 16 16 2 to 3pclk *5 0008 802bh wdt reset control/status register rstcsr 8 8 2 to 3pclk *5 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2 to 3pclk *5 0008 8032h iwdt iwdt control register iwdtcr 16 16 2 to 3pclk *5 0008 8034h iwdt iwdt status register iwdtsr 16 16 2 to 3pclk* 5 0008 8040h ada a/d data register a addra 16 16 2 to 3pclk* 5 0008 8042h ada a/d data register b addrb 16 16 2 to 3pclk* 5 0008 8044h ada a/d data register c addrc 16 16 2 to 3pclk* 5 0008 8046h ada a/d data register d addrd 16 16 2 to 3pclk* 5 0008 8048h ada a/d data register e addre 16 16 2 to 3pclk* 5 0008 804ah ada a/d data register f addrf 16 16 2 to 3pclk* 5 0008 804ch ada a/d data register g addrg 16 16 2 to 3pclk* 5 0008 804eh ada a/d data register h addrh 16 16 2 to 3pclk* 5 0008 8050h ada a/d control/status register adcsr 8 8 2 to 3pclk* 5 0008 8051h ada a/d control register adcr 8 8 2 to 3pclk* 5 0008 805bh ada a/d sampling state register adsstr 8 8 2 to 3pclk* 5 0008 805dh ada a/d self-diagnostic register addiagr 8 8 2 to 3pclk* 5 0008 8060h ada a/d data register i addri 16 16 2 to 3pclk* 5 0008 8062h ada a/d data register j addrj 16 16 2 to 3pclk* 5 0008 8064h ada a/d data register k addrk 16 16 2 to 3pclk* 5 0008 8066h ada a/d data register l addrl 16 16 2 to 3pclk* 5 0008 8070h ada a/d start trigger select register adstrgr 8 8 2 to 3pclk* 5 0008 8072h ada a/d data placement register addpr 8 8 2 to 3pclk* 5 0008 8240h sci0 serial mode register smr *1 8 8 2 to 3pclk* 5 0008 8241h sci0 bit rate register brr 8 8 2 to 3pclk* 5 0008 8242h sci0 serial control register scr *1 8 8 2 to 3pclk* 5 0008 8243h sci0 transmit data register tdr 8 8 2 to 3pclk* 5 0008 8244h sci0 serial status register ssr *1 8 8 2 to 3pclk* 5 0008 8245h sci0 receive data register rdr 8 8 2 to 3pclk* 5 0008 8246h sci0 smart card mode register scmr 8 8 2 to 3pclk* 5 0008 8247h sci0 serial extended mode register semr 8 8 2 to 3pclk* 5 0008 8240h smci0 serial mode register smr 8 8 2 to 3pclk* 5 0008 8241h smci0 bit rate register brr 8 8 2 to 3pclk* 5 0008 8242h smci0 serial control register scr 8 8 2 to 3pclk* 5 0008 8243h smci0 transmit data register tdr 8 8 2 to 3pclk* 5 table 4.1 list of i/o register s (address order) (8 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 42 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 8244h smci0 serial status register ssr 8 8 2 to 3pclk* 5 0008 8245h smci0 receive data register rdr 8 8 2 to 3pclk* 5 0008 8246h smci0 smart card mode register scmr 8 8 2 to 3pclk* 5 0008 8248h sci1 serial mode register smr *1 8 8 2 to 3pclk* 5 0008 8249h sci1 bit rate register brr 8 8 2 to 3pclk* 5 0008 824ah sci1 serial control register scr *1 8 8 2 to 3pclk* 5 0008 824bh sci1 transmit data register tdr 8 8 2 to 3pclk* 5 0008 824ch sci1 serial status register ssr *1 8 8 2 to 3pclk* 5 0008 824dh sci1 receive data register rdr 8 8 2 to 3pclk* 5 0008 824eh sci1 smart card mode register scmr 8 8 2 to 3pclk* 5 0008 824fh sci1 serial extended mode register semr 8 8 2 to 3pclk* 5 0008 8248h smci1 serial mode register smr 8 8 2 to 3pclk* 5 0008 8249h smci1 bit rate register brr 8 8 2 to 3pclk* 5 0008 824ah smci1 serial control register scr 8 8 2 to 3pclk* 5 0008 824bh smci1 transmit data register tdr 8 8 2 to 3pclk* 5 0008 824ch smci1 serial status register ssr 8 8 2 to 3pclk* 5 0008 824dh smci1 receive data register rdr 8 8 2 to 3pclk* 5 0008 824eh smci1 smart card mode register scmr 8 8 2 to 3pclk* 5 0008 8250h sci2 serial mode register smr *1 8 8 2 to 3pclk* 5 0008 8251h sci2 bit rate register brr 8 8 2 to 3pclk* 5 0008 8252h sci2 serial control register scr *1 8 8 2 to 3pclk* 5 0008 8253h sci2 transmit data register tdr 8 8 2 to 3pclk* 5 0008 8254h sci2 serial status register ssr *1 8 8 2 to 3pclk* 5 0008 8255h sci2 receive data register rdr 8 8 2 to 3pclk* 5 0008 8256h sci2 smart card mode register scmr 8 8 2 to 3pclk* 5 0008 8257h sci2 serial extended mode register semr 8 8 2 to 3pclk* 5 0008 8250h smci2 serial mode register smr *1 8 8 2 to 3pclk* 5 0008 8251h smci2 bit rate register brr 8 8 2 to 3pclk* 5 0008 8252h smci2 serial control register scr *1 8 8 2 to 3pclk* 5 0008 8253h smci2 transmit data register tdr 8 8 2 to 3pclk* 5 0008 8254h smci2 serial status register ssr *1 8 8 2 to 3pclk* 5 0008 8255h smci2 receive data register rdr 8 8 2 to 3pclk* 5 0008 8256h smci2 smart card mode register scmr 8 8 2 to 3pclk* 5 0008 8280h crc crc control register crccr 8 8 2 to 3pclk* 5 0008 8281h crc crc data input register crcdir 8 8 2 to 3pclk* 5 0008 8282h crc crc data output register crcdor 16 16 2 to 3pclk* 5 0008 8300h riic i 2 c bus control register 1 iccr1 8 8 2 to 3pclk* 5 0008 8301h riic i 2 c bus control register 2 iccr2 8 8 2 to 3pclk* 5 0008 8302h riic i 2 c bus mode register 1 icmr1 8 8 2 to 3pclk* 5 0008 8303h riic i 2 c bus mode register 2 icmr2 8 8 2 to 3pclk* 5 0008 8304h riic i 2 c bus mode register 3 icmr3 8 8 2 to 3pclk* 5 0008 8305h riic i 2 c bus function enable register icfer 8 8 2 to 3pclk* 5 0008 8306h riic i 2 c bus status enable register icser 8 8 2 to 3pclk* 5 0008 8307h riic i 2 c bus interrupt enable register icier 8 8 2 to 3pclk* 5 table 4.1 list of i/o register s (address order) (9 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 43 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 8308h riic i 2 c bus status register 1 icsr1 8 8 2 to 3pclk* 5 0008 8309h riic i 2 c bus status register 2 icsr2 8 8 2 to 3pclk* 5 0008 830ah riic slave address register l0 sarl0 8 8 2 to 3pclk* 5 0008 830bh riic slave address register u0 saru0 8 8 2 to 3pclk* 5 0008 830ch riic slave address register l1 sarl1 8 8 2 to 3pclk* 5 0008 830dh riic slave address register u1 saru1 8 8 2 to 3pclk* 5 0008 830eh riic slave address register l2 sarl2 8 8 2 to 3pclk* 5 0008 830fh riic slave address register u2 saru2 8 8 2 to 3pclk* 5 0008 8310h riic i 2 c bus bit rate low-level register icbrl 8 8 2 to 3pclk* 5 0008 8311h riic i 2 c bus bit rate high-level register icbrh 8 8 2 to 3pclk* 5 0008 8312h riic i 2 c bus transmit data register icdrt 8 8 2 to 3pclk* 5 0008 8313h riic i 2 c bus receive data register icdrr 8 8 2 to 3pclk* 5 0008 8380h rspi rspi control register spcr 8 8 2 to 3pclk* 5 0008 8381h rspi rspi slave select polarity register sslp 8 8 2 to 3pclk* 5 0008 8382h rspi rspi pin control register sppcr 8 8 2 to 3pclk* 5 0008 8383h rspi rspi status register spsr 8 8 2 to 3pclk* 5 0008 8384h rspi rspi data register spdr 16, 32 16, 32 2 to 3pclk* 5 0008 8388h rspi rspi sequence control register spscr 8 8 2 to 3pclk* 5 0008 8389h rspi rspi sequence status register spssr 8 8 2 to 3pclk* 5 0008 838ah rspi rspi bit rate register spbr 8 8 2 to 3pclk* 5 0008 838bh rspi rspi data control register spdcr 8 8 2 to 3pclk* 5 0008 838ch rspi rspi clock delay register spckd 8 8 2 to 3pclk* 5 0008 838dh rspi rspi slave select negation delay register sslnd 8 8 2 to 3pclk* 5 0008 838eh rspi rspi next-access delay register spnd 8 8 2 to 3pclk* 5 0008 838fh rspi rspi control register 2 spcr2 8 8 2 to 3pclk* 5 0008 8390h rspi rspi command register 0 spcmd0 16 16 2 to 3pclk* 5 0008 8392h rspi rspi command register 1 spcmd1 16 16 2 to 3pclk* 5 0008 8394h rspi rspi command register 2 spcmd2 16 16 2 to 3pclk* 5 0008 8396h rspi rspi command register 3 spcmd3 16 16 2 to 3pclk* 5 0008 8398h rspi rspi command register 4 spcmd4 16 16 2 to 3pclk* 5 0008 839ah rspi rspi command register 5 spcmd5 16 16 2 to 3pclk* 5 0008 839ch rspi rspi command register 6 spcmd6 16 16 2 to 3pclk* 5 0008 839eh rspi rspi command register 7 spcmd7 16 16 2 to 3pclk* 5 0008 9000h s12ad0 a/d control register adcsr 8 8 2 to 3pclk* 5 0008 9004h s12ad0 a/d channel select register adans 16 16 2 to 3pclk* 5 0008 900ah s12ad0 a/d programmable gain amplifier register adpg 16 16 2 to 3pclk* 5 0008 900eh s12ad0 a/d control extended register adcer 16 16 2 to 3pclk* 5 0008 9010h s12ad0 a/d start trigger select register adstrgr 16 16 2 to 3pclk* 5 0008 9012h s12ad comparator operating mode select register 0 adcmpmd0 16 16 2 to 3pclk* 5 0008 9014h s12ad comparator operating mode select register 1 adcmpmd1 16 16 2 to 3pclk* 5 0008 9016h s12ad comparator filter mode register 0 adcmpnr0 16 16 2 to 3pclk* 5 0008 9018h s12ad comparator filter mode register 1 adcmpnr1 16 16 2 to 3pclk* 5 0008 901ah s12ad comparator detection flag register adcmpfr 8 8 2 to 3pclk* 5 0008 901ch s12ad comparator interrupt select register adcmpsel 16 16 2 to 3pclk* 5 table 4.1 list of i/o register s (address order) (10 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 44 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 901eh s12ad0 a/d data register diag adrd 16 16 2 to 3pclk* 5 0008 9020h s12ad0 a/d data register 0a addr0a 16 16 2 to 3pclk* 5 0008 9022h s12ad0 a/d data register 1 addr1 16 16 2 to 3pclk* 5 0008 9024h s12ad0 a/d data register 2 addr2 16 16 2 to 3pclk* 5 0008 9026h s12ad0 a/d data register 3 addr3 16 16 2 to 3pclk* 5 0008 9030h s12ad0 a/d data register 0b addr0b 16 16 2 to 3pclk* 5 0008 9060h s12ad0 a/d sampling state register adsstr 8 8 2 to 3pclk* 5 0008 9080h s12ad1 a/d control register adcsr 8 8 2 to 3pclk* 5 0008 9084h s12ad1 a/d channel select register adans 16 16 2 to 3pclk* 5 0008 908ah s12ad1 a/d programmable gain amplifier register adpg 16 16 2 to 3pclk* 5 0008 908eh s12ad1 a/d control extended register adcer 16 16 2 to 3pclk* 5 0008 9090h s12ad1 a/d start trigger select register adstrgr 16 16 2 to 3pclk* 5 0008 909eh s12ad1 a/d data register diag adrd 16 16 2 to 3pclk* 5 0008 90a0h s12ad1 a/d data register 0a addr0a 16 16 2 to 3pclk* 5 0008 90a2h s12ad1 a/d data register 1 addr1 16 16 2 to 3pclk* 5 0008 90a4h s12ad1 a/d data register 2 addr2 16 16 2 to 3pclk* 5 0008 90a6h s12ad1 a/d data register 3 addr3 16 16 2 to 3pclk* 5 0008 90b0h s12ad1 a/d data register 0b addr0b 16 16 2 to 3pclk* 5 0008 90e0h s12ad1 a/d sampling state register adsstr 8 8 2 to 3pclk* 5 0008 c001h port1 data direction register ddr 8 8 2 to 3pclk* 5 0008 c002h port2 data direction register ddr 8 8 2 to 3pclk* 5 0008 c003h port3 data direction register ddr 8 8 2 to 3pclk* 5 0008 c007h port7 data direction register ddr 8 8 2 to 3pclk* 5 0008 c008h port8 data direction register ddr* 2*3 8 8 2 to 3pclk* 5 0008 c009h port9 data direction register ddr 8 8 2 to 3pclk* 5 0008 c00ah porta data direction register ddr 8 8 2 to 3pclk* 5 0008 c00bh portb data direction register ddr 8 8 2 to 3pclk* 5 0008 c00dh portd data direction register ddr 8 8 2 to 3pclk* 5 0008 c00eh porte data direction register ddr 8 8 2 to 3pclk* 5 0008 c010h portg data direction register ddr* 1 * 2*3 8 8 2 to 3pclk* 5 0008 c021h port1 data register dr 8 8 2 to 3pclk* 5 0008 c022h port2 data register dr 8 8 2 to 3pclk* 5 0008 c023h port3 data register dr 8 8 2 to 3pclk* 5 0008 c027h port7 data register dr 8 8 2 to 3pclk* 5 0008 c028h port8 data register dr* 2*3 8 8 2 to 3pclk* 5 0008 c029h port9 data register dr 8 8 2 to 3pclk* 5 0008 c02ah porta data register dr 8 8 2 to 3pclk* 5 0008 c02bh portb data register dr 8 8 2 to 3pclk* 5 0008 c02dh portd data register dr 8 8 2 to 3pclk* 5 0008 c02eh porte data register dr 8 8 2 to 3pclk* 5 0008 c030h portg data register dr* 1 * 2*3 8 8 2 to 3pclk* 5 0008 c041h port1 data register port 8 8 2 to 3pclk* 5 0008 c042h port2 data register port 8 8 2 to 3pclk* 5 0008 c043h port3 data register port 8 8 2 to 3pclk* 5 table 4.1 list of i/o register s (address order) (11 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 45 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 c044h port4 data register port 8 8 2 to 3pclk* 5 0008 c045h port5 data register port* 2*3 8 8 2 to 3pclk* 5 0008 c046h port6 data register port *3 8 8 2 to 3pclk* 5 0008 c047h port7 data register port 8 8 2 to 3pclk* 5 0008 c048h port8 data register port* 2*3 8 8 2 to 3pclk* 5 0008 c049h port9 data register port 8 8 2 to 3pclk* 5 0008 c04ah porta data register port 8 8 2 to 3pclk* 5 0008 c04bh portb data register port 8 8 2 to 3pclk* 5 0008 c04dh portd data register port 8 8 2 to 3pclk* 5 0008 c04eh porte data register port 8 8 2 to 3pclk* 5 0008 c050h portg port register port* 1 * 2*3 8 8 2 to 3pclk* 5 0008 c061h port1 input buffer control register icr 8 8 2 to 3pclk* 5 0008 c062h port2 input buffer control register icr 8 8 2 to 3pclk* 5 0008 c063h port3 input buffer control register icr 8 8 2 to 3pclk* 5 0008 c064h port4 input buffer control register icr 8 8 2 to 3pclk* 5 0008 c065h port5 input buffer control register icr* 2*3 8 8 2 to 3pclk* 5 0008 c066h port6 input buffer control register icr *3 8 8 2 to 3pclk* 5 0008 c067h port7 input buffer control register icr 8 8 2 to 3pclk* 5 0008 c068h port8 input buffer control register icr* 2*3 8 8 2 to 3pclk* 5 0008 c069h port9 input buffer control register icr 8 8 2 to 3pclk* 5 0008 c06ah porta input buffer control register icr 8 8 2 to 3pclk* 5 0008 c06bh portb input buffer control register icr 8 8 2 to 3pclk* 5 0008 c06dh portd input buffer control register icr 8 8 2 to 3pclk* 5 0008 c06eh porte input buffer control register icr 8 8 2 to 3pclk* 5 0008 c070h portg input buffer control register icr* 1 * 2*3 8 8 2 to 3pclk* 5 0008 c108h ioport port function register 8 pf8irq 8 8 2 to 3pclk* 5 0008 c109h ioport port function register 9 pf9irq 8 8 2 to 3pclk* 5 0008 c10ah ioport port function register a pfaadc 8 8 2 to 3pclk* 5 0008 c10ch ioport port function register c pfcmtu 8 8 2 to 3pclk* 5 0008 c10dh ioport port function register d pfdgpt 8 8 2 to 3pclk* 5 0008 c10fh ioport port function register f pffsci 8 8 2 to 3pclk* 5 0008 c110h ioport port function register g pfgspi 8 8 2 to 3pclk* 5 0008 c111h ioport port function register h pfhspi 8 8 2 to 3pclk* 5 0008 c113h ioport port function register j pfjcan 8 8 2 to 3pclk* 5 0008 c114h ioport port function register k pfklin 8 8 2 to 3pclk* 5 0008 c116h ioport port function register m pfmpoe 8 8 2 to 3pclk* 5 0008 c117h ioport port function register n pfnpoe 8 8 2 to 3pclk* 5 0008 c280h system deep standby control register dpsbycr 8 8 4 to 5pclk* 5 0008 c281h system deep standby wait control register dpswcr 8 8 4 to 5pclk* 5 0008 c282h system deep standby interrupt enable register dpsier 8 8 4 to 5pclk* 5 0008 c283h system deep standby interrupt flag register dpsifr 8 8 4 to 5pclk* 5 0008 c284h system deep standby interrupt edge register dpsiegr 8 8 4 to 5pclk* 5 0008 c285h system reset status register rstsr 8 8 4 to 5pclk* 5 0008 c289h flash flash write erase protection register fwepror 8 8 4 to 5pclk* 5 table 4.1 list of i/o register s (address order) (12 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 46 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 c28ch system key code register for low-voltage detection control register lvdkeyr 8 8 4 to 5pclk* 5 0008 c28dh system voltage detection control register lvdcr 8 8 4 to 5pclk* 5 0008 c290h system deep standby backup r egister 0 dpsbkr0 8 8 4 to 5pclk* 5 0008 c291h system deep standby backup r egister 1 dpsbkr1 8 8 4 to 5pclk* 5 0008 c292h system deep standby backup r egister 2 dpsbkr2 8 8 4 to 5pclk* 5 0008 c293h system deep standby backup r egister 3 dpsbkr3 8 8 4 to 5pclk* 5 0008 c294h system deep standby backup r egister 4 dpsbkr4 8 8 4 to 5pclk* 5 0008 c295h system deep standby backup r egister 5 dpsbkr5 8 8 4 to 5pclk* 5 0008 c296h system deep standby backup r egister 6 dpsbkr6 8 8 4 to 5pclk* 5 0008 c297h system deep standby backup r egister 7 dpsbkr7 8 8 4 to 5pclk* 5 0008 c298h system deep standby backup r egister 8 dpsbkr8 8 8 4 to 5pclk* 5 0008 c299h system deep standby backup r egister 9 dpsbkr9 8 8 4 to 5pclk* 5 0008 c29ah system deep standby backup r egister 10 dpsbkr10 8 8 4 to 5pclk* 5 0008 c29bh system deep standby backup r egister 11 dpsbkr11 8 8 4 to 5pclk* 5 0008 c29ch system deep standby backup r egister 12 dpsbkr12 8 8 4 to 5pclk* 5 0008 c29dh system deep standby backup r egister 13 dpsbkr13 8 8 4 to 5pclk* 5 0008 c29eh system deep standby backup r egister 14 dpsbkr14 8 8 4 to 5pclk* 5 0008 c29fh system deep standby backup r egister 15 dpsbkr15 8 8 4 to 5pclk* 5 0008 c2a0h system deep standby backup r egister 16 dpsbkr16 8 8 4 to 5pclk* 5 0008 c2a1h system deep standby backup r egister 17 dpsbkr17 8 8 4 to 5pclk* 5 0008 c2a2h system deep standby backup r egister 18 dpsbkr18 8 8 4 to 5pclk* 5 0008 c2a3h system deep standby backup r egister 19 dpsbkr19 8 8 4 to 5pclk* 5 0008 c2a4h system deep standby backup r egister 20 dpsbkr20 8 8 4 to 5pclk* 5 0008 c2a5h system deep standby backup r egister 21 dpsbkr21 8 8 4 to 5pclk* 5 0008 c2a6h system deep standby backup r egister 22 dpsbkr22 8 8 4 to 5pclk* 5 0008 c2a7h system deep standby backup r egister 23 dpsbkr23 8 8 4 to 5pclk* 5 0008 c2a8h system deep standby backup r egister 24 dpsbkr24 8 8 4 to 5pclk* 5 0008 c2a9h system deep standby backup r egister 25 dpsbkr25 8 8 4 to 5pclk* 5 0008 c2aah system deep standby backup r egister 26 dpsbkr26 8 8 4 to 5pclk* 5 0008 c2abh system deep standby backup r egister 27 dpsbkr27 8 8 4 to 5pclk* 5 0008 c2ach system deep standby backup r egister 28 dpsbkr28 8 8 4 to 5pclk* 5 0008 c2adh system deep standby backup r egister 29 dpsbkr29 8 8 4 to 5pclk* 5 0008 c2aeh system deep standby backup r egister 30 dpsbkr30 8 8 4 to 5pclk* 5 0008 c2afh system deep standby backup r egister 31 dpsbkr31 8 8 4 to 5pclk* 5 0008 c4c0h poe input level control/status register 1 icsr1 16 8, 16 2 to 3pclk* 5 0008 c4c2h poe output level control/status register 1 ocsr1 16 8, 16 2 to 3pclk* 5 0008 c4c4h poe input level control/status register 2 icsr2 16 8, 16 2 to 3pclk* 5 0008 c4c6h poe output level control/status register 2 ocsr2 16 8, 16 2 to 3pclk* 5 0008 c4c8h poe input level control/status register 3 icsr3 16 8, 16 2 to 3pclk* 5 0008 c4cah poe software port output enable register spoer 8 8 2 to 3pclk* 5 0008 c4cbh poe port output enable control register 1 poecr1 8 8 2 to 3pclk* 5 0008 c4cch poe port output enable control register 2 poecr2 16 16 2 to 3pclk* 5 0008 c4ceh poe port output enable control register 3 poecr3 16 16 2 to 3pclk* 5 table 4.1 list of i/o register s (address order) (13 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 47 of 92 apr 20, 2011 rx62t group 4. i/o registers 0008 c4d0h poe port output enable control register 4 poecr4 16 16 2 to 3pclk* 5 0008 c4d2h poe port output enable control register 5 poecr5 16 16 2 to 3pclk* 5 0008 c4d4h poe port output enable control register 6 poecr6 16 16 2 to 3pclk* 5 0008 c4d6h poe input level control/status register 4 icsr4 16 8, 16 2 to 3pclk* 5 0008 c4d8h poe input level control/status register 5 icsr5 16 8, 16 2 to 3pclk* 5 0008 c4dah poe active level setting register 1 alr1 16 8, 16 2 to 3pclk* 5 0009 0200h to 0009 03ffh can0 *4 mailbox registers 0 to 31 mb0 to mb 31 128 8, 16, 32 2 to 3pclk* 5 0009 0400h can0 *4 mask register 0 mkr0 32 8, 16, 32 2 to 3pclk* 5 0009 0404h can0 *4 mask register 1 mkr1 32 8, 16, 32 2 to 3pclk* 5 0009 0408h can0 *4 mask register 2 mkr2 32 8, 16, 32 2 to 3pclk* 5 0009 040ch can0 *4 mask register 3 mkr3 32 8, 16, 32 2 to 3pclk* 5 0009 0410h can0 *4 mask register 4 mkr4 32 8, 16, 32 2 to 3pclk* 5 0009 0414h can0 *4 mask register 5 mkr5 32 8, 16, 32 2 to 3pclk* 5 0009 0418h can0 *4 mask register 6 mkr6 32 8, 16, 32 2 to 3pclk* 5 0009 041ch can0 *4 mask register 7 mkr7 32 8, 16, 32 2 to 3pclk* 5 0009 0420h can0 *4 fifo received id compare register 0 fidcr0 32 8, 16, 32 2 to 3pclk* 5 0009 0424h can0 *4 fifo received id compare register 1 fidcr1 32 8, 16, 32 2 to 3pclk* 5 0009 0428h can0 *4 mask invalid register mkivlr 32 8, 16, 32 2 to 3pclk* 5 0009 042ch can0 *4 mailbox interrupt enable register mier 32 8, 16, 32 2 to 3pclk* 5 0009 0820h to 0009 083fh can0 *4 message control registers 0 to 31 mctl0 to mctl31 8 8 2 to 3pclk* 5 0009 0840h can0 *4 control register ctlr 16 8, 16 2 to 3pclk* 5 0009 0842h can0 *4 status register str 16 8, 16 2 to 3pclk* 5 0009 0844h can0 *4 bit configuration register bcr 32 8, 16, 32 2 to 3pclk* 5 0009 0848h can0 *4 receive fifo control register rfcr 8 8 2 to 3pclk* 5 0009 0849h can0 *4 receive fifo pointer control register rfpcr 8 8 2 to 3pclk* 5 0009 084ah can0 *4 transmit fifo control register tfcr 8 8 2 to 3pclk* 5 0009 084bh can0 *4 transmit fifo pointer control register tfpcr 8 8 2 to 3pclk* 5 0009 084ch can0 *4 error interrupt enable register eier 8 8 2 to 3pclk* 5 0009 084dh can0 *4 error interrupt factor judge register eifr 8 8 2 to 3pclk* 5 0009 084eh can0 *4 receive error count register recr 8 8 2 to 3pclk* 5 0009 084fh can0 *4 transmit error count register tecr 8 8 2 to 3pclk* 5 0009 0850h can0 *4 error code store register ecsr 8 8 2 to 3pclk* 5 0009 0851h can0 *4 channel search support register cssr 8 8 2 to 3pclk* 5 0009 0852h can0 *4 mailbox search status register mssr 8 8 2 to 3pclk* 5 0009 0853h can0 *4 mailbox search mode register msmr 8 8 2 to 3pclk* 5 0009 0854h can0 *4 time stamp register tsr 16 8, 16 2 to 3pclk* 5 0009 0856h can0 *4 acceptance filter support register afsr 16 8, 16 2 to 3pclk* 5 0009 0858h can0 *4 test control register tcr 8 8 2 to 3pclk* 5 0009 4001h lin0 lin wake-up baud rate select register lwbr 8 8 2 to 3pclk* 5 0009 4002h lin0 lin baud rate prescaler 0 register lbrp0 8 8, 16 2 to 3pclk* 5 0009 4003h lin0 lin baud rate prescaler 1 register lbrp1 8 8, 16 2 to 3pclk* 5 table 4.1 list of i/o register s (address order) (14 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 48 of 92 apr 20, 2011 rx62t group 4. i/o registers 0009 4004h lin0 lin self-test control register lstc 8 8 2 to 3pclk* 5 0009 4008h lin0 mode register l0md 8 8, 16, 32 2 to 3pclk* 5 0009 4009h lin0 break field setting register l0brk 8 8, 16, 32 2 to 3pclk* 5 0009 400ah lin0 space setting register l0spc 8 8, 16, 32 2 to 3pclk* 5 0009 400bh lin0 wake-up setting register l0wup 8 8, 16, 32 2 to 3pclk* 5 0009 400ch lin0 interrupt enable register l0ie 8 8, 16 2 to 3pclk* 5 0009 400dh lin0 error detection enable register l0ede 8 8, 16 2 to 3pclk* 5 0009 400eh lin0 control register l0c 8 8 2 to 3pclk* 5 0009 4010h lin0 transmission control register l0tc 8 8, 16, 32 2 to 3pclk* 5 0009 4011h lin0 mode status register l0mst 8 8, 16, 32 2 to 3pclk* 5 0009 4012h lin0 status register l0st 8 8, 16, 32 2 to 3pclk* 5 0009 4013h lin0 error status register l0est 8 8, 16, 32 2 to 3pclk* 5 0009 4014h lin0 response field set register l0rfc 8 8, 16 2 to 3pclk* 5 0009 4015h lin0 buffer register l0idb 8 8, 16 2 to 3pclk* 5 0009 4016h lin0 check sum buffer register l0cbr 8 8 2 to 3pclk* 5 0009 4018h lin0 data 1 buffer register l0db1 8 8, 16, 32 2 to 3pclk* 5 0009 4019h lin0 data 2 buffer register l0db2 8 8, 16, 32 2 to 3pclk* 5 0009 401ah lin0 data 3 buffer register l0db3 8 8, 16, 32 2 to 3pclk* 5 0009 401bh lin0 data 4 buffer register l0db4 8 8, 16, 32 2 to 3pclk* 5 0009 401ch lin0 data 5 buffer register l0db5 8 8, 16, 32 2 to 3pclk* 5 0009 401dh lin0 data 6 buffer register l0db6 8 8, 16, 32 2 to 3pclk* 5 0009 401eh lin0 data 7 buffer register l0db7 8 8, 16, 32 2 to 3pclk* 5 0009 401fh lin0 data 8 buffer register l0db8 8 8, 16, 32 2 to 3pclk* 5 000c 1200h mtu3 timer control register tcr 8 8, 16, 32 5iclk 000c 1201h mtu4 timer control register tcr 8 8 5iclk 000c 1202h mtu3 timer mode register 1 tmdr1 8 8, 16 5iclk 000c 1203h mtu4 timer mode register 1 tmdr1 8 8 5iclk 000c 1204h mtu3 timer i/o control register h tiorh 8 8, 16, 32 5iclk 000c 1205h mtu3 timer i/o control register l tiorl 8 8 5iclk 000c 1206h mtu4 timer i/o control register h tiorh 8 8, 16 5iclk 000c 1207h mtu4 timer i/o control register l tiorl 8 8 5iclk 000c 1208h mtu3 timer interrupt enable register tier 8 8, 16 5iclk 000c 1209h mtu4 timer interrupt enable register tier 8 8 5iclk 000c 120ah mtu timer output master enable register a toera 8 8 5iclk 000c 120dh mtu timer gate control register a tgcra 8 8 5iclk 000c 120eh mtu timer output control register 1a tocr1a 8 8, 16 5iclk 000c 120fh mtu timer output control register 2a tocr2a 8 8 5iclk 000c 1210h mtu3 timer counter tcnt 16 16, 32 5iclk 000c 1212h mtu4 timer counter tcnt 16 16 5iclk 000c 1214h mtu timer cycle data register a tcdra 16 16, 32 5iclk 000c 1216h mtu timer dead time data register a tddra 16 16 5iclk 000c 1218h mtu3 timer general register a tgra 16 16, 32 5iclk 000c 121ah mtu3 timer general register b tgrb 16 16 5iclk 000c 121ch mtu4 timer general register a tgra 16 16, 32 5iclk table 4.1 list of i/o register s (address order) (15 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 49 of 92 apr 20, 2011 rx62t group 4. i/o registers 000c 121eh mtu4 timer general register b tgrb 16 16 5iclk 000c 1220h mtu timer subcounter a tcntsa 16 16, 32 5iclk 000c 1222h mtu timer cycle buffer register a tcbra 16 16 5iclk 000c 1224h mtu3 timer general register c tgrc 16 16, 32 5iclk 000c 1226h mtu3 timer general register d tgrd 16 16 5iclk 000c 1228h mtu4 timer general register c tgrc 16 16, 32 5iclk 000c 122ah mtu4 timer general register d tgrd 16 16 5iclk 000c 122ch mtu3 timer status register tsr 8 8, 16 5iclk 000c 122dh mtu4 timer status register tsr 8 8 5iclk 000c 1230h mtu timer interrupt skipping set register 1a titcr1a 8 8, 16 5iclk 000c 1231h mtu timer interrupt skipping counter 1a titcnt1a 8 8 5iclk 000c 1232h mtu timer buffer transfer set register a tbtera 8 8 5iclk 000c 1234h mtu timer dead time enable register a tdera 8 8 5iclk 000c 1236h mtu timer output level buffer register a tolbra 8 8 5iclk 000c 1238h mtu3 timer buffer operation transfer mode register tbtm 8 8, 16 5iclk 000c 1239h mtu4 timer buffer operation transfer mode register tbtm 8 8 5iclk 000c 123ah mtu timer interrupt skipping mode register a titmra 8 8 5iclk 000c 123bh mtu timer interrupt skipping set register 2a titcr2a 8 8 5iclk 000c 123ch mtu timer interrupt skipping counter 2a titcnt2a 8 8 5iclk 000c 1240h mtu4 timer a/d converter start request control register tadcr 16 16 5iclk 000c 1244h mtu4 timer a/d converter start request cycle set register a tadcora 16 16, 32 5iclk 000c 1246h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 5iclk 000c 1248h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16, 32 5iclk 000c 124ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 5iclk 000c 1260h mtu timer waveform control register a twcra 8 8 5iclk 000c 1270h mtu3 timer mode register 2a tmdr2a 8 8 5iclk 000c 1272h mtu3 timer general register e tgre 16 16 5iclk 000c 1274h mtu4 timer general register e tgre 16 16 5iclk 000c 1276h mtu4 timer general register f tgrf 16 16 5iclk 000c 1280h mtu timer start register a tstra 8 8, 16 5iclk 000c 1281h mtu timer synchronous register a tsyra 8 8 5iclk 000c 1282h mtu timer counter synchronous start register tcsystr 8 8 5iclk 000c 1284h mtu timer read/write enable register a trwera 8 8 5iclk 000c 1300h mtu0 timer control register tcr 8 8, 16, 32 5iclk 000c 1301h mtu0 timer mode register 1 tmdr1 8 8 5iclk 000c 1302h mtu0 timer i/o control register h tiorh 8 8, 16 5iclk 000c 1303h mtu0 timer i/o control register l tiorl 8 8 5iclk 000c 1304h mtu0 timer interrupt enable register tier 8 8, 16, 32 5iclk 000c 1305h mtu0 timer status register tsr 8 8 5iclk 000c 1306h mtu0 timer counter tcnt 16 16 5iclk 000c 1308h mtu0 timer general register a tgra 16 16, 32 5iclk table 4.1 list of i/o register s (address order) (16 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 50 of 92 apr 20, 2011 rx62t group 4. i/o registers 000c 130ah mtu0 timer general register b tgrb 16 16 5iclk 000c 130ch mtu0 timer general register c tgrc 16 16, 32 5iclk 000c 130eh mtu0 timer general register d tgrd 16 16 5iclk 000c 1320h mtu0 timer general register e tgre 16 16, 32 5iclk 000c 1322h mtu0 timer general register f tgrf 16 16 5iclk 000c 1324h mtu0 timer interrupt enable register 2 tier2 8 8, 16 5iclk 000c 1325h mtu0 timer status register 2 tsr2 8 8 5iclk 000c 1326h mtu0 timer buffer operation transfer mode register tbtm 8 8 5iclk 000c 1380h mtu1 timer control register tcr 8 8, 16 5iclk 000c 1381h mtu1 timer mode register 1 tmdr1 8 8 5iclk 000c 1382h mtu1 timer i/o control register tior 8 8 5iclk 000c 1384h mtu1 timer interrupt enable register tier 8 8, 16, 32 5iclk 000c 1385h mtu1 timer status register tsr 8 8 5iclk 000c 1386h mtu1 timer counter tcnt 16 16 5iclk 000c 1388h mtu1 timer general register a tgra 16 16, 32 5iclk 000c 138ah mtu1 timer general register b tgrb 16 16 5iclk 000c 1390h mtu1 timer input capture control register ticcr 8 8 5iclk 000c 1400h mtu2 timer control register tcr 8 8, 16 5iclk 000c 1401h mtu2 timer mode register 1 tmdr1 8 8 5iclk 000c 1402h mtu2 timer i/o control register tior 8 8 5iclk 000c 1404h mtu2 timer interrupt enable register tier 8 8, 16, 32 5iclk 000c 1405h mtu2 timer status register tsr 8 8 5iclk 000c 1406h mtu2 timer counter tcnt 16 16 5iclk 000c 1408h mtu2 timer general register a tgra 16 16, 32 5iclk 000c 140ah mtu2 timer general register b tgrb 16 16 5iclk 000c 1a00h mtu6 timer control register tcr 8 8, 16, 32 5iclk 000c 1a01h mtu7 timer control register tcr 8 8 5iclk 000c 1a02h mtu6 timer mode register 1 tmdr1 8 8, 16 5iclk 000c 1a03h mtu7 timer mode register 1 tmdr1 8 8 5iclk 000c 1a04h mtu6 timer i/o control register h tiorh 8 8, 16, 32 5iclk 000c 1a05h mtu6 timer i/o control register l tiorl 8 8 5iclk 000c 1a06h mtu7 timer i/o control register h tiorh 8 8, 16 5iclk 000c 1a07h mtu7 timer i/o control register l tiorl 8 8 5iclk 000c 1a08h mtu6 timer interrupt enable register tier 8 8, 16 5iclk 000c 1a09h mtu7 timer interrupt enable register tier 8 8 5iclk 000c 1a0ah mtu timer output master enable register b toerb 8 8 5iclk 000c 1a0eh mtu timer output control register 1b tocr1b 8 8, 16 5iclk 000c 1a0fh mtu timer output control register 2b tocr2b 8 8 5iclk 000c 1a10h mtu6 timer counter tcnt 16 16, 32 5iclk 000c 1a12h mtu7 timer counter tcnt 16 16 5iclk 000c 1a14h mtu timer cycle data register b tcdrb 16 16, 32 5iclk 000c 1a16h mtu timer dead time data register b tddrb 16 16 5iclk 000c 1a18h mtu6 timer general register a tgra 16 16, 32 5iclk 000c 1a1ah mtu6 timer general register b tgrb 16 16 5iclk table 4.1 list of i/o register s (address order) (17 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 51 of 92 apr 20, 2011 rx62t group 4. i/o registers 000c 1a1ch mtu7 timer general register a tgra 16 16, 32 5iclk 000c 1a1eh mtu7 timer general register b tgrb 16 16 5iclk 000c 1a20h mtu timer subcounter b tcntsb 16 16, 32 5iclk 000c 1a22h mtu timer cycle buffer register b tcbrb 16 16 5iclk 000c 1a24h mtu6 timer general register c tgrc 16 16, 32 5iclk 000c 1a26h mtu6 timer general register d tgrd 16 16 5iclk 000c 1a28h mtu7 timer general register c tgrc 16 16, 32 5iclk 000c 1a2ah mtu7 timer general register d tgrd 16 16 5iclk 000c 1a2ch mtu6 timer status register tsr 8 8, 16 5iclk 000c 1a2dh mtu7 timer status register tsr 8 8 5iclk 000c 1a30h mtu timer interrupt skipping set register 1b titcr1b 8 8, 16 5iclk 000c 1a31h mtu timer interrupt skipping counter 1b titcnt1b 8 8 5iclk 000c 1a32h mtu timer buffer transfer set register b tbterb 8 8 5iclk 000c 1a34h mtu timer dead time enable register b tderb 8 8 5iclk 000c 1a36h mtu timer output level buffer register b tolbrb 8 8 5iclk 000c 1a38h mtu6 timer buffer operation transfer mode register tbtm 8 8, 16 5iclk 000c 1a39h mtu7 timer buffer operation transfer mode register tbtm 8 8 5iclk 000c 1a3ah mtu timer interrupt skipping mode register b titmrb 8 8 5iclk 000c 1a3bh mtu timer interrupt skipping set register 2b titcr2b 8 8 5iclk 000c 1a3ch mtu timer interrupt skipping counter 2b titcnt2b 8 8 5iclk 000c 1a40h mtu7 timer a/d converter start request control register tadcr 16 16 5iclk 000c 1a44h mtu7 timer a/d converter start request cycle set register a tadcora 16 16, 32 5iclk 000c 1a46h mtu7 timer a/d converter start request cycle set register b tadcorb 16 16 5iclk 000c 1a48h mtu7 timer a/d converter start request cycle set buffer register a tadcobra 16 16, 32 5iclk 000c 1a4ah mtu7 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 5iclk 000c 1a50h mtu6 timer synchronous clear register tsycr 8 8 5iclk 000c 1a60h mtu timer waveform control register b twcrb 8 8 5iclk 000c 1a70h mtu timer mode register 2b tmdr2b 8 8 5iclk 000c 1a72h mtu6 timer general register e tgre 16 16 5iclk 000c 1a74h mtu7 timer general register e tgre 16 16 5iclk 000c 1a76h mtu7 timer general register f tgrf 16 16 5iclk 000c 1a80h mtu timer start register b tstrb 8 8, 16 5iclk 000c 1a81h mtu timer synchronous register b tsyrb 8 8 5iclk 000c 1a84h mtu timer read/write enable register b trwerb 8 8 5iclk 000c 1c80h mtu5 timer counter u tcntu 16 16, 32 5iclk 000c 1c82h mtu5 timer general register u tgru 16 16 5iclk 000c 1c84h mtu5 timer control register u tcru 8 8 5iclk 000c 1c86h mtu5 timer i/o control register u tioru 8 8 5iclk 000c 1c90h mtu5 timer counter v tcntv 16 16, 32 5iclk 000c 1c92h mtu5 timer general register v tgrv 16 16 5iclk 000c 1c94h mtu5 timer control register v tcrv 8 8 5iclk table 4.1 list of i/o register s (address order) (18 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 52 of 92 apr 20, 2011 rx62t group 4. i/o registers 000c 1c96h mtu5 timer i/o control register v tiorv 8 8 5iclk 000c 1ca0h mtu5 timer counter w tcntw 16 16, 32 5iclk 000c 1ca2h mtu5 timer general register w tgrw 16 16 5iclk 000c 1ca4h mtu5 timer control register w tcrw 8 8 5iclk 000c 1ca6h mtu5 timer i/o control register w tiorw 8 8 5iclk 000c 1cb0h mtu5 timer status register tsr 8 8 5iclk 000c 1cb2h mtu5 timer interrupt enable register tier 8 8 5iclk 000c 1cb4h mtu5 timer start register tstr 8 8 5iclk 000c 1cb6h mtu5 timer compare match clear register tcntcmpc lr 8 8 5iclk 000c 2000h gpt general pwm timer software start register gtstr 16 8, 16, 32 3 to 5iclk *6 000c 2004h gpt general pwm timer hardware source start control register gthscr 16 8, 16, 32 3 to 5iclk *6 000c 2006h gpt general pwm timer hardware source clear control register gthccr 16 8, 16, 32 3 to 5iclk *6 000c 2008h gpt general pwm timer hardware start source select register gthssr 16 8, 16, 32 3 to 5iclk *6 000c 200ah gpt general pwm timer hardware stop/clear source select register gthpsr 16 8, 16, 32 3 to 5iclk *6 000c 200ch gpt general pwm timer write-protection register gtwp 16 8, 16, 32 3 to 5iclk *6 000c 200eh gpt general pwm timer sync register gtsync 16 8, 16, 32 3 to 5iclk *6 000c 2010h gpt general pwm timer external trigger input interrupt register gtetint 16 8, 16, 32 3 to 5iclk *6 000c 2014h gpt general pwm timer buffer operation disable register gtbdr 16 8, 16, 32 3 to 5iclk *6 000c 2080h gpt loco count control register lccr 16 8, 16, 32 3 to 5iclk *6 000c 2082h gpt loco count status register lcst 16 8, 16, 32 3 to 5iclk *6 000c 2084h gpt loco count value register lcnt 16 8, 16, 32 3 to 5iclk *6 000c 2086h gpt loco count result average register lcnta 16 8, 16, 32 3 to 5iclk *6 000c 2088h gpt loco count result register 0 lcnt00 16 8, 16, 32 3 to 5iclk *6 000c 208ah gpt loco count result register 1 lcnt01 16 8, 16, 32 3 to 5iclk *6 000c 208ch gpt loco count result register 2 lcnt02 16 8, 16, 32 3 to 5iclk *6 000c 208eh gpt loco count result register 3 lcnt03 16 8, 16, 32 3 to 5iclk *6 000c 2090h gpt loco count result register 4 lcnt04 16 8, 16, 32 3 to 5iclk *6 000c 2092h gpt loco count result register 5 lcnt05 16 8, 16, 32 3 to 5iclk *6 000c 2094h gpt loco count result register 6 lcnt06 16 8, 16, 32 3 to 5iclk *6 000c 2096h gpt loco count result register 7 lcnt07 16 8, 16, 32 3 to 5iclk *6 '000c 2098h gpt loco count result register 8 lcnt08 16 8, 16, 32 3 to 5iclk *6 000c 209ah gpt loco count result register 9 lcnt09 16 8, 16, 32 3 to 5iclk *6 000c 209ch gpt loco count result register 10 lcnt10 16 8, 16, 32 3 to 5iclk *6 000c 209eh gpt loco count result register 11 lcnt11 16 8, 16, 32 3 to 5iclk *6 000c 20a0h gpt loco count result register 12 lcnt12 16 8, 16, 32 3 to 5iclk *6 000c 20a2h gpt loco count result register 13 lcnt13 16 8, 16, 32 3 to 5iclk *6 000c 20a4h gpt loco count result register 14 lcnt14 16 8, 16, 32 3 to 5iclk *6 000c 20a6h gpt loco count result register 15 lcnt15 16 8, 16, 32 3 to 5iclk *6 000c 20a8h gpt loco count upper permissible deviation register lcntdu 16 8, 16, 32 3 to 5iclk *6 table 4.1 list of i/o register s (address order) (19 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 53 of 92 apr 20, 2011 rx62t group 4. i/o registers 000c 20aah gpt loco count lower permissible deviation register lcntdl 16 8, 16, 32 3 to 5iclk *6 000c 2100h gpt0 general pwm timer i/o control register gtior 16 8, 16, 32 3 to 5iclk *6 000c 2102h gpt0 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 3 to 5iclk *6 000c 2104h gpt0 general pwm timer control register gtcr 16 8, 16, 32 3 to 5iclk *6 000c 2106h gpt0 general pwm timer buffer enable register gtber 16 8, 16, 32 3 to 5iclk *6 000c 2108h gpt0 general pwm timer count direct ion register gtudc 16 8, 16, 32 3 to 5iclk *6 000c 210ah gpt0 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 3 to 5iclk *6 000c 210ch gpt0 general pwm timer status register gtst 16 8, 16, 32 3 to 5iclk *6 000c 210eh gpt0 general pwm timer counter gtcnt 16 16 3 to 5iclk *6 000c 2110h gpt0 general pwm timer compare capture register a gtccra 16 16, 32 3 to 5iclk *6 000c 2112h gpt0 general pwm timer compare capture register b gtccrb 16 16, 32 3 to 5iclk *6 000c 2114h gpt0 general pwm timer compare capture register c gtccrc 16 16, 32 3 to 5iclk *6 000c 2116h gpt0 general pwm timer compare capture register d gtccrd 16 16, 32 3 to 5iclk *6 000c 2118h gpt0 general pwm timer compare capture register e gtccre 16 16, 32 3 to 5iclk *6 000c 211ah gpt0 general pwm timer compare capture register f gtccrf 16 16, 32 3 to 5iclk *6 000c 211ch gpt0 general pwm timer cycle setting register gtpr 16 16, 32 3 to 5iclk *6 000c 211eh gpt0 general pwm timer cycle setting buffer register gtpbr 16 16, 32 3 to 5iclk *6 000c 2120h gpt0 general pwm timer cycle setting double-buffer register gtpdbr 16 16, 32 3 to 5iclk *6 000c 2124h gpt0 a/d converter start request timing register a gtadtra 16 16, 32 3 to 5iclk *6 000c 2126h gpt0 a/d converter start request timing buffer register a gtadtbra 16 16, 32 3 to 5iclk *6 000c 2128h gpt0 a/d converter start request timing double-buffer register a gtadtdbra 16 16, 32 3 to 5iclk *6 000c 212ch gpt0 a/d converter start request timing register b gtadtrb 16 16, 32 3 to 5iclk *6 000c 212eh gpt0 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 3 to 5iclk *6 000c 2130h gpt0 a/d converter start request timing double-buffer register b gtadtdbrb 16 16, 32 3 to 5iclk *6 000c 2134h gpt0 general pwm timer output negate control register gtoncr 16 16, 32 3 to 5iclk *6 000c 2136h gpt0 general pwm timer dead time control register gtdtcr 16 16, 32 3 to 5iclk *6 000c 2138h gpt0 general pwm timer dead time value register gtdvu 16 16, 32 3 to 5iclk *6 000c 213ah gpt0 general pwm timer dead time value register gtdvd 16 16, 32 3 to 5iclk *6 000c 213ch gpt0 general pwm timer dead time buffer register gtdbu 16 16, 32 3 to 5iclk *6 000c 213eh gpt0 general pwm timer dead time buffer register gtdbd 16 16, 32 3 to 5iclk *6 000c 2140h gpt0 general pwm time r output protection function status register gtsos 16 16, 32 3 to 5iclk *6 000c 2142h gpt0 general pwm time r output protection function temporary release register gtsotr 16 16, 32 3 to 5iclk *6 000c 2180h gpt1 general pwm timer i/o control register gtior 16 8, 16, 32 3 to 5iclk *6 000c 2182h gpt1 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 3 to 5iclk *6 000c 2184h gpt1 general pwm timer control register gtcr 16 8, 16, 32 3 to 5iclk *6 000c 2186h gpt1 general pwm timer buffer enable register gtber 16 8, 16, 32 3 to 5iclk *6 table 4.1 list of i/o register s (address order) (20 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 54 of 92 apr 20, 2011 rx62t group 4. i/o registers 000c 2188h gpt1 general pwm timer count direct ion register gtudc 16 8, 16, 32 3 to 5iclk *6 000c 218ah gpt1 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 3 to 5iclk *6 000c 218ch gpt1 general pwm timer status register gtst 16 8, 16, 32 3 to 5iclk *6 000c 218eh gpt1 general pwm timer counter gtcnt 16 16 3 to 5iclk *6 000c 2190h gpt1 general pwm timer compare capture register a gtccra 16 16, 32 3 to 5iclk *6 000c 2192h gpt1 general pwm timer compare capture register b gtccrb 16 16, 32 3 to 5iclk *6 000c 2194h gpt1 general pwm timer compare capture register c gtccrc 16 16, 32 3 to 5iclk *6 000c 2196h gpt1 general pwm timer compare capture register d gtccrd 16 16, 32 3 to 5iclk *6 000c 2198h gpt1 general pwm timer compare capture register e gtccre 16 16, 32 3 to 5iclk *6 000c 219ah gpt1 general pwm timer compare capture register f gtccrf 16 16, 32 3 to 5iclk *6 000c 219ch gpt1 general pwm timer cycle se tting register gtpr 16 16, 32 3 to 5iclk *6 000c 219eh gpt1 general pwm timer cycle setting buffer register gtpbr 16 16, 32 3 to 5iclk *6 000c 21a0h gpt1 general pwm timer cycle setting double-buffer register gtpdbr 16 16, 32 3 to 5iclk *6 000c 21a4h gpt1 a/d converter start request timing register a gtadtra 16 16, 32 3 to 5iclk *6 000c 21a6h gpt1 a/d converter start request timing buffer register a gtadtbra 16 16, 32 3 to 5iclk *6 000c 21a8h gpt1 a/d converter start request timing double-buffer register a gtadtdbra 16 16, 32 3 to 5iclk *6 000c 21ach gpt1 a/d converter start request timing register b gtadtrb 16 16, 32 3 to 5iclk *6 000c 21aeh gpt1 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 3 to 5iclk *6 000c 21b0h gpt1 a/d converter start request timing double-buffer register b gtadtdbrb 16 16, 32 3 to 5iclk *6 000c 21b4h gpt1 general pwm timer output negate control register gtoncr 16 16, 32 3 to 5iclk *6 000c 21b6h gpt1 general pwm timer dead time control register gtdtcr 16 16, 32 3 to 5iclk *6 000c 21b8h gpt1 general pwm timer dead time value register gtdvu 16 16, 32 3 to 5iclk *6 000c 21bah gpt1 general pwm timer dead time value register gtdvd 16 16, 32 3 to 5iclk *6 000c 21bch gpt1 general pwm timer dead time buffer register gtdbu 16 16, 32 3 to 5iclk *6 000c 21beh gpt1 general pwm timer dead time buffer register gtdbd 16 16, 32 3 to 5iclk *6 000c 21c0h gpt1 general pwm timer output protection function status register gtsos 16 16, 32 3 to 5iclk *6 000c 21c2h gpt1 general pwm timer output protection temporary release register gtsotr 16 16, 32 3 to 5iclk *6 000c 2200h gpt2 general pwm timer i/o control register gtior 16 8, 16, 32 3 to 5iclk *6 000c 2202h gpt2 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 3 to 5iclk *6 000c 2204h gpt2 general pwm timer control register gtcr 16 8, 16, 32 3 to 5iclk *6 000c 2206h gpt2 general pwm timer buffer enable register gtber 16 8, 16, 32 3 to 5iclk *6 000c 2208h gpt2 general pwm timer count direct ion register gtudc 16 8, 16, 32 3 to 5iclk *6 000c 220ah gpt2 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 3 to 5iclk *6 000c 220ch gpt2 general pwm timer status register gtst 16 8, 16, 32 3 to 5iclk *6 000c 220eh gpt2 general pwm timer counter gtcnt 16 16 3 to 5iclk *6 000c 2210h gpt2 general pwm timer compare capture register a gtccra 16 16, 32 3 to 5iclk *6 table 4.1 list of i/o register s (address order) (21 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 55 of 92 apr 20, 2011 rx62t group 4. i/o registers 000c 2212h gpt2 general pwm timer compare capture register b gtccrb 16 16, 32 3 to 5iclk *6 000c 2214h gpt2 general pwm timer compare capture register c gtccrc 16 16, 32 3 to 5iclk *6 000c 2216h gpt2 general pwm timer compare capture register d gtccrd 16 16, 32 3 to 5iclk *6 000c 2218h gpt2 general pwm timer compare capture register e gtccre 16 16, 32 3 to 5iclk *6 000c 221ah gpt2 general pwm timer compare capture register f gtccrf 16 16, 32 3 to 5iclk *6 000c 221ch gpt2 general pwm timer cycle se tting register gtpr 16 16, 32 3 to 5iclk *6 000c 221eh gpt2 general pwm timer cycle setting buffer register gtpbr 16 16, 32 3 to 5iclk *6 000c 2220h gpt2 general pwm timer cycle setting double-buffer register gtpdbr 16 16, 32 3 to 5iclk *6 000c 2224h gpt2 a/d converter start request timing register a gtadtra 16 16, 32 3 to 5iclk *6 000c 2226h gpt2 a/d converter start request timing buffer register a gtadtbra 16 16, 32 3 to 5iclk *6 000c 2228h gpt2 a/d converter start request timing double-buffer register a gtadtdbra 16 16, 32 3 to 5iclk *6 000c 222ch gpt2 a/d converter start request timing register b gtadtrb 16 16, 32 3 to 5iclk *6 000c 222eh gpt2 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 3 to 5iclk *6 000c 2230h gpt2 a/d converter start request timing double-buffer register b gtadtdbrb 16 16, 32 3 to 5iclk *6 000c 2234h gpt2 general pwm timer output negate control register gtoncr 16 16, 32 3 to 5iclk *6 000c 2236h gpt2 general pwm timer dead time control register gtdtcr 16 16, 32 3 to 5iclk *6 000c 2238h gpt2 general pwm timer dead time value register gtdvu 16 16, 32 3 to 5iclk *6 000c 223ah gpt2 general pwm timer dead time value register gtdvd 16 16, 32 3 to 5iclk *6 000c 223ch gpt2 general pwm timer dead time buffer register gtdbu 16 16, 32 3 to 5iclk *6 000c 223eh gpt2 general pwm timer dead time buffer register gtdbd 16 16, 32 3 to 5iclk *6 000c 2240h gpt2 general pwm time r output protection function status register gtsos 16 16, 32 3 to 5iclk *6 000c 2242h gpt2 general pwm timer output protection temporary release register gtsotr 16 16, 32 3 to 5iclk *6 000c 2280h gpt3 general pwm timer i/o control register gtior 16 8, 16, 32 3 to 5iclk *6 000c 2282h gpt3 general pwm timer interrupt output setting register gtintad 16 8, 16, 32 3 to 5iclk *6 000c 2284h gpt3 general pwm timer control register gtcr 16 8, 16, 32 3 to 5iclk *6 000c 2286h gpt3 general pwm timer buffer enable register gtber 16 8, 16, 32 3 to 5iclk *6 000c 2288h gpt3 general pwm timer count direct ion register gtudc 16 8, 16, 32 3 to 5iclk *6 000c 228ah gpt3 general pwm timer interrupt and a/d converter start request skipping setting register gtitc 16 8, 16, 32 3 to 5iclk *6 000c 228ch gpt3 general pwm timer status register gtst 16 8, 16, 32 3 to 5iclk *6 000c 228eh gpt3 general pwm timer counter gtcnt 16 16 3 to 5iclk *6 000c 2290h gpt3 general pwm timer compare capture register a gtccra 16 16, 32 3 to 5iclk *6 000c 2292h gpt3 general pwm timer compare capture register b gtccrb 16 16, 32 3 to 5iclk *6 000c 2294h gpt3 general pwm timer compare capture register c gtccrc 16 16, 32 3 to 5iclk *6 000c 2296h gpt3 general pwm timer compare capture register d gtccrd 16 16, 32 3 to 5iclk *6 000c 2298h gpt3 general pwm timer compare capture register e gtccre 16 16, 32 3 to 5iclk *6 000c 229ah gpt3 general pwm timer compare capture register f gtccrf 16 16, 32 3 to 5iclk *6 000c 229ch gpt3 general pwm timer cycle se tting register gtpr 16 16, 32 3 to 5iclk *6 table 4.1 list of i/o register s (address order) (22 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 56 of 92 apr 20, 2011 rx62t group 4. i/o registers note 1. this register is not su pported by the 100-pin lqfp version. note 2. this register is not su pported by the 80-pin lqfp version. 000c 229eh gpt3 general pwm timer cycle setting buffer register gtpbr 16 16, 32 3 to 5iclk *6 000c 22a0h gpt3 general pwm timer cycle setting double-buffer register gtpdbr 16 16, 32 3 to 5iclk *6 000c 22a4h gpt3 a/d converter start request timing register a gtadtra 16 16, 32 3 to 5iclk *6 000c 22a6h gpt3 a/d converter start request timing buffer register a gtadtbra 16 16, 32 3 to 5iclk *6 000c 22a8h gpt3 a/d converter start request timing double-buffer register a gtadtdbra 16 16, 32 3 to 5iclk *6 000c 22ach gpt3 a/d converter start request timing register b gtadtrb 16 16, 32 3 to 5iclk *6 000c 22aeh gpt3 a/d converter start request timing buffer register b gtadtbrb 16 16, 32 3 to 5iclk *6 000c 22b0h gpt3 a/d converter start request timing double-buffer register b gtadtdbrb 16 16, 32 3 to 5iclk *6 000c 22b4h gpt3 general pwm timer output negate control register gtoncr 16 16, 32 3 to 5iclk *6 000c 22b6h gpt3 general pwm timer dead time control register gtdtcr 16 16, 32 3 to 5iclk *6 000c 22b8h gpt3 general pwm timer dead time value register gtdvu 16 16, 32 3 to 5iclk *6 000c 22bah gpt3 general pwm timer dead time value register gtdvd 16 16, 32 3 to 5iclk *6 000c 22bch gpt3 general pwm timer dead time buffer register gtdbu 16 16, 32 3 to 5iclk *6 000c 22beh gpt3 general pwm timer dead time buffer register gtdbd 16 16, 32 3 to 5iclk *6 000c 22c0h gpt3 general pwm timer output protection function status register gtsos 16 16, 32 3 to 5iclk *6 000c 22c2h gpt3 general pwm timer output protection temporary release register gtsotr 16 16, 32 3 to 5iclk *6 007f c402h flash flash mode register fmodr 8 8 2 to 3pclk *5 007f c410h flash flash access status register fastat 8 8 2 to 3pclk *5 007f c411h flash flash access error interrupt enable register faeint 8 8 2 to 3pclk *5 007f c412h flash flash ready interrupt enable register frdyie 8 8 2 to 3pclk *5 007f c440h flash data flash read enable register 0 dflre0 16 16 2 to 3pclk *5 007f c442h flash data flash read enable register 1 dflre1 16 16 2 to 3pclk *5 007f c450h flash data flash programming/erasure enable register 0 dflwe0 16 16 2 to 3pclk *5 007f c452h flash data flash programming/erasure enable register 1 dflwe1 16 16 2 to 3pclk *5 007f c454h flash fcu ram enable register fcurame 16 16 2 to 3pclk *5 007f ffb0h flash flash status register 0 fstatr0 8 8 2 to 3pclk *5 007f ffb1h flash flash status register 1 fstatr1 8 8 2 to 3pclk *5 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 to 3pclk *5 007f ffb4h flash flash protect register fprotr 16 16 2 to 3pclk *5 007f ffb6h flash flash reset register fresetr 16 16 2 to 3pclk *5 007f ffbah flash fcu command register fcmdr 16 16 2 to 3pclk *5 007f ffc8h flash fcu processing switching register fcpsr 16 16 2 to 3pclk *5 007f ffcah flash data flash blank check control register dflbccnt 16 16 2 to 3pclk *5 007f ffcch flash flash p/e status register fpestat 16 16 2 to 3pclk *5 007f ffceh flash data flash blank check status register dflbcstat 16 16 2 to 3pclk *5 007f ffe8h flash peripheral clock notification register pckar 16 16 2 to 3pclk *5 table 4.1 list of i/o register s (address order) (23 / 23) address module abbreviation register name register abbreviation number of bits access size number of access cycles
r01ds0096ej0100 rev.1.00 page 57 of 92 apr 20, 2011 rx62t group 4. i/o registers note 3. this register is not su pported by the 64-pin lqfp version. note 4. this register is not supported by the product without the can function. note 5. the number of access states depends on the number of divided cycles for clock sy nchronization (0 to 1 pclk). note 6. reading the registers takes 3 cycles of iclk and writing to the registers takes 5 cycles of iclk.
r01ds0096ej0100 rev.1.00 page 58 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. note 1. when the a/d converter is not in use, do not leave the avcc0, vrefh0, vrefl0, avss0, avcc, vref, and avss pins open. connect the avcc0, vrefh0, avcc, and vref pins to vcc, and the avss0, vrefl0, and avss pins to vss, respectively. table 5.1 absolute maximum ratings item symbol value unit power supply voltage vcc pllvcc -0.3 to +6.5 v input voltage (except for ports 4 to 6) v in -0.3 to vcc+0.3 v input voltage (port 4) v in -0.3 to avcc0+0.3 v input voltage (ports 5 and 6) v in -0.3 to avcc+0.3 v analog power supply voltage avcc0, avcc *1 -0.3 to +6.5 v reference power supply voltage vrefh0 *1 -0.3 to avcc0+0.3 v vref *1 -0.3 to avcc+0.3 analog input voltage (port 4) v an -0.3 to avcc0+0.3 v analog input voltage (ports 5 and 6) v an -0.3 to avcc+0.3 v operating temperature t opr -40 to +85 ? c storage temperature t stg -55 to +125 ? c
r01ds0096ej0100 rev.1.00 page 59 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.2 dc characteristics table 5.2 dc characteristics (1) (1 / 3) note: items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions schmitt trigger input voltage can input pin irq input pin mtu3 input pin poe3 input pin sci input pin a/d trigger input pin nmi input pin gpt input pin lin input pin res# v ih vcc ? 0.8 - vcc+0.3 v v il -0.3 - vcc ? 0.2 v t vcc ? 0.06 -- riic input pin (iicbus) v ih vcc ? 0.7 - vcc+0.3 v il -0.3 - vcc ? 0.3 v t vcc ? 0.05 -- port 4* 1 (also usable as an analog port) v ih avcc0 ? 0.8 - avcc0 +0.3 v il - 0.3 - avcc0 ? 0.2 v t avcc0 ? 0.06 -- ports 5 and 6* 1 (also usable as analog ports) v ih avcc ? 0.8 -avcc +0.3 v il -0.3 - avcc ? 0.2 v t avcc ? 0.06 -- ports 1 to 3* 1 ports 7 to b* 1 ports d, e, and g* 1 v ih vcc ? 0.8 - vcc+0.3 v il -0.3 - vcc ? 0.2 v t vcc ? 0.06 -- input high voltage (except schmitt trigger input pin) md pin, emle v ih vcc ? 0.9 - vcc+0.3 v extal rspi input pin vcc ? 0.8 vcc+0.3 riic input pin (smbus) 2.1 vcc+0.3 conditions 1 and 2 input low voltage (except schmitt trigger input pin) md pin, emle v il -0.3 - vcc ? 0.1 v extal rspi input pin -0.3 - vcc ? 0.2 riic input pin (smbus) -0.3 - 0.8 conditions 1 and 2
r01ds0096ej0100 rev.1.00 page 60 of 92 apr 20, 2011 rx62t group 5. electrical characteristics output high voltage all output pins (except for p71 to p76 and p90 to p95) v oh vcc-0.5 - - v i oh = -1 ma p71 to p76 vcc-0.5 - - i oh = -1ma 64-pin lqfp condition 3 vcc-1.0 - - i oh = -5ma 64-pin lqfp other than condition 3 p90 to p95 vcc-0.5 - - i oh = -1ma 80-pin lqfp or 64-pin lqfp vcc-1.0 - - i oh = -5 ma 112-pin lqfp or 100-pin lqfp output low voltage all output pins (except for p71 to p76, p90 to p95, and riic) v ol - - 0.5 v i ol = 1.0 ma p71 to p76 - - 0.5 i ol = 1.0 ma 64-pin lqfp other than condition 3 --1.1 i ol = 15 ma conditions 1 and 2 --1 . 4 i ol = 15 ma other than 64-pin lqfp condition 3 p90 to p95 - - 0.5 i ol = 1.0 ma 80-pin lqfp or 64-pin lqfp --1.1 i ol = 15 ma 112-pin lqfp or 100-pin lqfp conditions 1 and 2 --1.4 i ol = 1 ma 112-pin lqfp or 100-pin lqfp condition 3 riic pin - - 0.4 i ol = 3 ma --0 . 6 i ol = 6 ma input leakage current res#, md pin, emle ? i in ? - - 1.0 ? av in = 0 v, v in = vcc three-state leakage current (off state) ports 1 to a, pb0, pb3 to pb7, d, e, g ? i tsi ? - - 1.0 ? av in = 0 v, v in = vcc ports pb1 and pb2 - - 5.0 table 5.2 dc characteristics (1) (2 / 3) note: items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions
r01ds0096ej0100 rev.1.00 page 61 of 92 apr 20, 2011 rx62t group 5. electrical characteristics note 1. this includes the multiplexed input pins, except in cases where port pins pb1 and pb2 are used as riic input pins or por t pins p22 to p24, p30, pa3 to pa5, pb0, pd0 to pd2, or pd6 are used as rspi input pins. input capacitance all input pins (except for ports pb1 and pb2) c in - - 15 pf v in = 0 v, f = 1 mhz, t a = 25 ? c ports pb1 and pb2 - - 30 table 5.2 dc characteristics (1) (3 / 3) note: items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions
r01ds0096ej0100 rev.1.00 page 62 of 92 apr 20, 2011 rx62t group 5. electrical characteristics note 1. supply current values ar e with all output pins unloaded. note 2. measured with clocks s upplied to the peripheral functions. th is does not include the bgo operation. note 3. i cc depends on f (iclk) as follows. (iclk : pclk = 8:4) icc max. = 0.54 x f + 16 (max.) icc max. = 0.14 x f + 6 (normal operation) icc max. = 0.44 x f + 16 (sleep mode) note 4. measured with clocks not supplied to the peripheral functions. this does not include the bgo operation. note 5. incremented if data is written to or erased from t he rom or data flash for data storage during the program execution. note 6. the values are for reference. table 5.3 dc characteristics (2) note: items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions supply current *1 in operation max. *2 i cc *3 - - 70 ma iclk = 100 mhz pclk = 50 mhz normal *4 -35- increased by bgo operation *5 -15- sleep 22 60 all-module-clock-stop mode *6 14 28 standby mode software standby mode - 0.10 3 ma deep software standby mode -2060 ? a analog power supply current during 12-bit a/d conversion (when a sample-and-hold circuit is in use; per unit) ai cc0 -35ma during 12-bit a/d conversion (when a sample-and-hold circuit is not in use; per unit) -35ma programmable gain amp (per channel) - 1 2 ma window comparator (1 channel) 0.5 1 ma window comparator (6 channels) - 1 2 ma during 12-bit a/d conversion (per unit) - 60 90 ? a during 10-bit a/d conversion (per unit) ai cc -0.92ma waiting for 10-bit a/d conversion (all units) - 0.3 3 ? a reference power supply current during 12-bit a/d conversion (per unit) ai refh0 -1.63ma waiting for 12-bit a/d conversion (all units) - 1.6 3 ma during 10-bit a/d conversion (per unit) ai ref -0.11ma waiting for 10-bit a/d conversion (all units) - 0.1 3 ? a vcc rising gradient sv cc --20ms/v
r01ds0096ej0100 rev.1.00 page 63 of 92 apr 20, 2011 rx62t group 5. electrical characteristics caution: to protect the lsi's reliability, the output current values should not exceed the permissible output current. note 1. i ol = 15 ma (max.)/ - i oh = 5 ma (max.) for p71 to p76 and p90 to p95. note, however, that up to 6 (112-pin or 100-pin lqfp) or 3 (80-pin or 64-pin lqfp) pins can accept over 2.0-ma i ol / - i oh at the same time. table 5.4 permissible output currents note: items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit permissible output low current (average value per pin) i ol --2 . 0 *1 ma permissible output low current (max. value per pin) i ol --4 . 0 *1 ma permissible output low current (total) i ol --1 1 0m a permissible output high current (average value per pin) - i oh --2 . 0 *1 ma permissible output high current (max. value per pin) - i oh --4 . 0 *1 ma permissible output high current (total) - i oh --3 5m a
r01ds0096ej0100 rev.1.00 page 64 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.3 ac characteristics 5.3.1 clock timing table 5.5 operation frequency value note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit operating frequency system clock (iclk) f 8 - 100 mhz peripheral module clock (pclk) 8 - 50 table 5.6 clock timing note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = ? 40 to +85 ? c. ta is the same under conditions 1 to 3. item symbol min. max. unit test conditions oscillation settling time after reset (crystal) t osc1 10 - ms figure 5.1 oscillation settling time afte r leaving software standby mode (crystal) t osc2 10 - ms figure 5.2 oscillation settling time after leaving deep software standby mode (crystal) t osc3 10 - ms figure 5.3 extal external clock output delay settling time t dext 1 - ms figure 5.1 extal external clock input low pulse width t exl 35 - ns figure 5.4 extal external clock input high pulse width t exh 35 - ns extal external clock rising time t exr -5n s extal external clock falling time t exf -5n s on-chip oscillator (iwd tclk) oscillation frequency f iwdtclk 62.5 187.5 khz
r01ds0096ej0100 rev.1.00 page 65 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.1 oscillation settling timing figure 5.2 oscillation settling timing after software standby mode t osc1 t dext vcc extal res# iclk software standby mode (power-down mode) irq exception handling irqmd[1:0] = 10b ssby = 1 wait instruction oscillation settling time t osc2 irq exception handling 01 10 ssby irqcrn.irqmd[1:0] irq iclk oscillator
r01ds0096ej0100 rev.1.00 page 66 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.3 oscillation settling timing after deep software standby mode invalid by the internal reset irq exception handling dirqneg = 1 ssby = 1 deep software standby mode (power-down mode) reset exception handling oscillation settling time t osc3 wait instruction when iokeep=l operating when iokeep=h oscillator iclk irq irq interrupt dirqnf set request set dirqneg bit set dpsby bit set iokeep bit cleared set l i/o port operating retained iokeep bit i/o port operating retained operating dpsrstf flag internal reset l h
r01ds0096ej0100 rev.1.00 page 67 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.4 extal external input clock timing t exf vcc0.5 extal t exh t exl t exr
r01ds0096ej0100 rev.1.00 page 68 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.3.2 control signal timing note 1. do not allow a reset by the signal on the res# pin during programming or erasure of the rom or data-flash memory or duri ng blank checking of the data-flash memory. for details, see sect ion 30.12, usage notes in section 30, rom (flash memory for code storage). note 2. both the time and the number of cycles should satisfy the specifications. note 3. this is to specify the fcu reset and the wdt reset. note 4. iclk cycles. figure 5.5 reset input timing figure 5.6 nmi interrupt input timing figure 5.7 irq interrupt input timing table 5.7 control signal timing note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = ? 40 to +85 ? c. ta is the same under conditions 1 to 3. item symbol min. max. unit test conditions res# pulse width (except for programming or eras ure of the rom or data-flash memory or blank checking of the data-flash memory* 1 ) t resw * 2 20 - t icyc * 4 figure 5.5 1.5 - ? s internal reset time* 3 t resw2 35 - ? s nmi pulse width t nmiw 200 - ns figure 5.6 irq pulse width t irqw 200 - ns figure 5.7 res# t resw nmi t nmiw irq t irqw
r01ds0096ej0100 rev.1.00 page 69 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.3.3 timing of on-chi p peripheral modules note: ? t pcyc : pclk cycle figure 5.8 sck clock input timing figure 5.9 sci input/output timing: clock synchronous mode table 5.8 timing of on-chip peripheral modules (1) note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = ? 40 to +85 ? c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit sci input clock cycle asynchronous t scyc 4 ? t pcyc - ns figure 5.8 clock synchronous 6 ? t pcyc - input clock pulse width t sckw 0.4 ? t pcyc 0.6 ? t scyc ns input clock rise time t sckr -2 0n s input clock fall time t sckf -2 0n s output clock cycle asynchronous t scyc 4 ? t pcyc -n s clock synchronous 6 ? t pcyc -n s output clock pulse width t sckw 0.4 ? t scyc 0.6 ? t scyc ns output clock rise time t sckr -2 0n s output clock fall time t sckf -2 0n s transmit data delay time (clock synchronous) t txd - 40 ns figure 5.9 receive data setup time (clock synchronous) t rxs 40 - ns receive data hold time (clock synchronous) t rxh 40 - ns t sckw t sckr t sckf t scyc sckn (n = 0 to 2) t txd t rxs t rxh txdn rxdn sckn n = 0 to 2
r01ds0096ej0100 rev.1.00 page 70 of 92 apr 20, 2011 rx62t group 5. electrical characteristics note: ? t iiccyc : cycles of internal base clock (iic ) for the riic module note 1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. note 2. cb indicates the total capacity of the bus line. table 5.9 timing of on-chip peripheral modules (2) note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = ? 40 to +85 ? c. ta is the same under conditions 1 to 3. item symbol min.* 1 * 2 max. unit test conditions riic (standard mode) scl input cycle time t scl 6(12) ?? t llccyc + 1300 - ns figure 5.10 scl input high pulse width t sclh 3(6) ? t llccyc + 300 - ns scl input low pulse width t scll 3(6) ? t llccyc + 1000 - ns scl, sda input rising time t sr - 1000 ns scl, sda input falling time t sf - 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) ?? t llccyc ns sda input bus free time t buf 3(6) ? t llccyc + 300 - ns start condition input hold time t stah t llccyc + 300 - ns re-start condition input setup time t stas 1000 - ns stop condition input setup time t stos 1000 - ns data input setup time t sdas t llccyc + 50 - ns data input hold time t sdah 0-n s scl, sda capacitive load c b - 400 pf riic (fast mode) scl input cycle time t scl 6(12) ?? t llccyc + 600 - ns scl input high pulse width t sclh 3(6) ? t llccyc + 300 - ns scl input low pulse width t scll 3(6) ? t llccyc + 300 - ns scl, sda input rising time t sr 20 + 0.1c b 300 ns scl, sda input falling time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) ?? t llccyc ns sda input bus free time t buf 3(6) ? t llccyc + 300 - ns start condition input hold time t stah t llccyc + 300 - ns re-start condition input setup time t stas 300 - ns stop condition input setup time t stos 300 - ns data input setup time t sdas t llccyc + 50 - ns data input hold time t sdah 0-n s scl, sda capacitive load c b - 400 pf
r01ds0096ej0100 rev.1.00 page 71 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.10 i2c bus interface input/output timing sda scl v ih v il t stah t sclh t scll p * 1 s * 1 t sf t sr t scl t sdah t sdas t stas t sp t stos p * 1 t buf note 1: s, p, and sr indicate the following conditions. s: start condition p: stop condition sr: restart condition test conditions v ih = v cc 0.7, v il = v cc 0.3 v ol = 0.6 v, i ol = 6 ma (icfer.fmpe = 0) v ol = 0.4 v, i ol = 15 ma (icfer.fmpe = 1) sr * 1
r01ds0096ej0100 rev.1.00 page 72 of 92 apr 20, 2011 rx62t group 5. electrical characteristics note: ? note 1: t pcyc : pclk cycle table 5.10 timing of on-chip peripheral modules (3) note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = ? 40 to +85 ? c. ta is the same under conditions 1 to 3. item symbol min. max. unit test conditions rspi rspck clock cycle master t spcyc 4 4096 t pcyc figure 5.11 slave 8 4096 rspck clock high pulse width master t spckwh (t spcyc - t spckr - t spckf ) / 2-3 -ns slave (t spcyc - t spckr - t spckf ) / 2 - rspck clock low pulse width master t spckwl (t spcyc - t spckr - t spckf ) / 2-3 -ns slave (t spcyc - t spckr - t spckf ) / 2 - rspck clock rise/fall time output t spckr t spckf -5n s input - 1 ? s data input setup time master t su 25 - ns figure 5.12 to figure 5.15 slave 0 - data input hold time master t h 0-n s slave 20+2 ? t pcyc - ssl setup time master t lead 18t spcyc slave 4 - t pcyc ssl hold time master t lag 18t spcyc slave 4 - t pcyc data output delay time master t od -2 0n s slave - 3 ? t pcyc +40 data output hold time master t oh 0-n s slave 0 - sucessive transmission delay time master t td t spcyc +2 ? t pcyc 8 ? t spcyc +2 ? t pcyc ns slave 4 ? t pcyc - mosi, miso rise/fall time output t dr t df - 15 ns figure 5.12 to figure 5.15 input - 1 ? s ssl rise/fall time output t sslr t sslf -1 5n s input - 1 ? s slave access time t sa -4t pcyc figure 5.12 to figure 5.15 slave output release time t rel -3t pcyc
r01ds0096ej0100 rev.1.00 page 73 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.11 rspi clock timing figure 5.12 rspi timing (master, cpha = 0) rspck master select output rspck slave select output t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc ssl0 to ssl3 output rspck cpol=0 output rspck cpol=1 output miso input mosi output t dr t df t su t h t lead t td t lag t sslr t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out
r01ds0096ej0100 rev.1.00 page 74 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.13 rspi timing (master, cpha = 1) figure 5.14 rspi timi ng (slave, cpha = 0) ssl0 to ssl3 output rspck cpol=0 output rspck cpol=1 output miso input mosi output t dr t df t su t h t lead t td t lag t sslr t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od ssl0 input rspck cpol=0 input rspck cpol=1 input mosi input miso output t dr t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel
r01ds0096ej0100 rev.1.00 page 75 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.15 rspi timi ng (slave, cpha = 1) ssl0 input rspck cpol=0 input rspck cpol=1 input miso output mosi input t dr t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out
r01ds0096ej0100 rev.1.00 page 76 of 92 apr 20, 2011 rx62t group 5. electrical characteristics note: ? t icyc : iclk cycle figure 5.16 mtu3 input/output timing figure 5.17 mtu3 clock input timing table 5.11 timing of on-chip peripheral modules (4) note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = ? 40 to +85 ? c. ta is the same under conditions 1 to 3. item symbol min. max. unit test conditions mtu3 input capture input pulse width (single-edge setting) t ticw 3.0 - t icyc figure 5.16 input capture input pulse width (both-edge setting) t ticw 5.0 - t icyc timer clock pulse width (single-edge setting) t tckwh/l 3.0 - t icyc figure 5.17 timer clock pulse width (both-edge setting) t tckwh/l 5.0 - t icyc timer clock pulse width (phase coefficient mode) t tckwh/l 5.0 - t icyc gpt input capture input pulse width (single-edge setting) t gticw 3.0 - t icyc figure 5.18 input capture input pulse width (both-edge setting) t gticw 5.0 - t icyc input capture input iclk t ticw mtclka to mtclkd iclk t tckwl t tckwh
r01ds0096ej0100 rev.1.00 page 77 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.18 gpt input/output timing note: ? t pcyc : pclk cycle figure 5.19 poe3# clock timing table 5.12 timing of on-chip peripheral modules (5) note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. max. unit test conditions poe3 poe# input pulse width t poew 1.5 - t pcyc figure 5.19 input capture input iclk t gticw poen# input pclk t poew
r01ds0096ej0100 rev.1.00 page 78 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.4 a/d conversion characteristics note 1. the conversion time includes the sampling time and the co mparison time. as the test condi tions, the number of sampling s tates is indicated. table 5.13 10-bit a/d conversion characteristics note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc ta = -40 to +85c item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time* 1 (ad clock = 25-mhz operation) 2.0 - - ? s sampling 25 states analog input capacitance - - 4 pf integral nonlinearity error - - ? 3.0 lsb offset error - - ? 3.0 lsb full-scale error - - ? 3.0 lsb quantization error - ? 0.5 - lsb absolute accuracy - - ? 4.0 lsb permissible signal source impedance - - 1.0 k ? condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item min. typ. max. unit test conditions resolution 10 10 10 bit conversion time* 1 (ad clock = 50-mhz operation) 1.0 - - ? s sampling 25 states analog input capacitance - - 4 pf integral nonlinearity error - - ? 3.0 lsb offset error - - ? 3.0 lsb full-scale error - - ? 3.0 lsb quantization error - ? 0.5 - lsb absolute accuracy - - ? 4.0 lsb permissible signal source impedance - - 1.0 k ?
r01ds0096ej0100 rev.1.00 page 79 of 92 apr 20, 2011 rx62t group 5. electrical characteristics note 1. the conversion time includes the sampling time and the co mparison time. as the test condi tions, the number of sampling s tates is indicated. table 5.14 12-bit a/d conversion characteristics note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc ta = -40 to +85c, iclk = 8 to 100 mhz, pclk = 8 to 50 mhz item min. typ. max. unit test conditions resolution 12 12 12 bit conversion time* 1 (ad clock = 25-mhz operation) 2.0 - - ? s sampling 20 states analog input capacitance - - 6 pf integral nonlinearity error - - ? 4.0 lsb offset error - - ? 7.5 lsb full-scale error - - ? 7.5 lsb quantization error - ? 0.5 - lsb absolute accuracy when a sample-and-hold circuit is in use -- ? 8.0 lsb avin = 0.25 to av refh - 0.25 when a sample-and-hold circuit is not in use -- ? 8.0 lsb avin = av refl to av refh permissible signal source impedance - - 3.0 k ? condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. iclk = 8 to 100 mhz, pclk = 8 to 50 mhz. item min. typ. max. unit test conditions resolution 12 12 12 bit conversion time* 1 (ad clock = 25-mhz operation) 1.0 - - ? s sampling 20 states analog input capacitance - - 6 pf integral nonlinearity error - - ? 4.0 lsb offset error - - ? 7.5 lsb full-scale error - - ? 7.5 lsb quantization error - ? 0.5 - lsb absolute accuracy when a sample-and-hold circuit is in use -- ? 8.0 lsb avin = 0.25 to av refh - 0.25 when a sample-and-hold circuit is not in use -- ? 8.0 lsb avin = av refl to av refh permissible signal source impedance - - 3.0 k ?
r01ds0096ej0100 rev.1.00 page 80 of 92 apr 20, 2011 rx62t group 5. electrical characteristics table 5.15 programmable gain amp characteristics note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions analog input capacitance cin - - 6 pf input offset voltage voff - - 8 mv input voltage range (vin) gain ? 2.000 vin 0.050 x avcc - 0.38 x avcc v gain ? 2.500 0.047 x avcc - 0.30 x avcc gain ? 3.077 0.045 x avcc - 0.24 x avcc gain ? 3.636 0.042 x avcc - 0.21 x avcc gain ? 4.000 0.040 x avcc - 0.19 x avcc gain ? 4.444 0.036 x avcc - 0.17 x avcc gain ? 5.000 0.033 x avcc - 0.15 x avcc gain ? 5.714 0.031 x avcc - 0.13 x avcc gain ? 6.667 0.029 x avcc - 0.11 x avcc gain ? 10.000 0.025 x avcc - 0.08 x avcc gain ? 13.333 0.023 x avcc - 0.06 x avcc slew rate sr 10 - - v/ ? s gain error gain ? 2.000 - - - 1 % gain ? 2.500 - - 1 gain ? 3.077 - - 1 gain ? 3.636 - - 1.5 gain ? 4.000 - - 1.5 gain ? 4.444 - - 2 gain ? 5.000 - - 2 gain ? 5.714 - - 2 gain ? 6.667 - - 3 gain ? 10.000 - - 4 gain ? 13.333 - - 4
r01ds0096ej0100 rev.1.00 page 81 of 92 apr 20, 2011 rx62t group 5. electrical characteristics table 5.16 comparator characteristics note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions analog input capacitance cin - - 6 pf refh pin offset voltage voff - - 5 mv refl pin offset voltage - - 5 mv refh input voltage range vin 1.7 - avcc ? 0.3 v refl input voltage range 0.3 - avcc ? 1.7 v refh reply time tcr - - 1 ? s refl reply time tcf - - 1 ? s
r01ds0096ej0100 rev.1.00 page 82 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.5 power-on reset circui t, voltage detection ci rcuit characteristics note 1. the power-off time indicates the time when vcc is below the minimum value of voltage detection levels v por, v det1, and v det2 for the por/ lvd. figure 5.20 power-on reset timing table 5.17 power-on reset circuit, voltage detection circuit characteristics note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 2.48 2.60 2.72 v figure 5.20 voltage detection circuit (lvd) vdet1 2.68 2.80 2.92 figure 5.21 vdet2 2.98 3.10 3.22 figure 5.22 internal reset time t por 20 35 50 ms figure 5.21 and figure 5.22 min. vcc down time *1 t voff 200 - - us figure 5.20 to figure 5.22 reply delay time tdet - - 200 us condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 3.70 3.90 4.10 v figure 5.20 voltage detection circuit (lvd) vdet1 3.95 4.15 4.35 figure 5.21 vdet2 4.40 4.60 4.80 figure 5.22 internal reset time t por 20 35 50 ms figure 5.21 and figure 5.22 min. vcc down time *1 t voff 200 - - us figure 5.20 to figure 5.22 reply delay time tdet - - 200 us internal reset signal (low valid) vcc t voff v por t por t por t det
r01ds0096ej0100 rev.1.00 page 83 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.21 voltage detection circ uit timing (vdet1) figure 5.22 voltage detection circ uit timing (vdet2) vcc v det1 t voff t por t det internal reset signal (low valid) vcc v det2 t voff t por t det internal reset signal (low valid)
r01ds0096ej0100 rev.1.00 page 84 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.6 oscillation stop detection timing figure 5.23 oscillation stop detection timing table 5.18 oscillation stop detection circuit characteristics note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions detection time tdr - - 1.0 ms figure 5.23 internal oscillat ion frequency when oscillation stop is detected f main 0.5 - 7.0 mhz iclk main clock oscillator internal oscillation normal operation abnormal operation ostdf * note : * this indicates the ostdf flag in the oscillation detection control register (ostdcr). t dr
r01ds0096ej0100 rev.1.00 page 85 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.7 rom (flash memory for code storage) characteristics note 1. definition of rewrite/erase cycle: the rewrite/erase cycle is the number of erasing for each block. when the rewrite/er ase cycle is n times (n = 1000), erasing ca n be performed n times for each block. for instance, when 256-byte writing is performed 16 times for different addresses in 4- kbyte block and then the entire block is erased, the rewrite/eras e cycle is counted as one. however, writing to the same addres s for several times as one erasing is not enabled (overwriting is prohibited). note 2. this indicates the minimum number that guarantees the char acteristics after rewriting. (t he guaranteed value is in the r ange from one to the minimum number.) note 3. this indicates the characteristic when rewrite is performed within the s pecification range including the minimum number. table 5.19 rom (flash memory for code storage) characteristics note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc temperature range for the programming/erasure operation: ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions programming time 256 bytes t p256 - 2 12 ms pclk = 50 mhz n pec ? 100 4 kbytes t p4k - 2 35 0m s 16 kbytes t p16k - 90 200 ms 256 byte t p256 - 2.4 14.4 ms pclk = 50 mhz n pec > 100 4 kbytes t p4k - 27.6 60 ms 16 kbytes t p16k - 108 240 ms erasure time 4 kbytes t e4k - 2 56 0m sp c l k = 5 0 m h z n pec ? 100 16 kbytes t e16k - 100 240 ms 4 kbytes t e4k - 3 07 2m sp c l k = 5 0 m h z n pec > 100 16 kbytes t e16k - 120 288 ms rewrite/erase cycle *1 n pec 1000 *2 --times suspend delay time during writing t spd - - 120 ? s figure 5.24 pclk = 50 mhz first suspend delay time during erasing (in suspend priority mode) t sesd1 - - 120 ? s second suspend delay time during erasing (in suspend priority mode) t sesd2 --1 . 7m s suspend delay time during erasing (in erasure priority mode) t seed --1 . 7m s data hold time *3 t drp 10 - - year
r01ds0096ej0100 rev.1.00 page 86 of 92 apr 20, 2011 rx62t group 5. electrical characteristics 5.8 data flash (flash memory fo r data storage) characteristics note 1. definition of rewrite/erase cycle: the rewrite/erase cycle is the number of er asing for each block. when the rewrite/eras e cycle is n times (n = 30000), erasing c an be performed n times for each block. for instance, when 128-byte writing is performed 16 times for different addresses in 2- kbyte block and then the entire block is erased, the rewrite/eras e cycle is counted as one. however, writing to the same addres s for several times as one erasing is not enabled (overwriting is prohibited). note 2. this indicates the minimum number that guarantees the char acteristics after rewriting. (t he guaranteed value is in the r ange from one to the minimum number.) note 3. this indicates the characteristic when rewrite is performed within the s pecification range including the minimum number. table 5.20 data flash (flash memory for data storage) characteristics note:items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. condition 1: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 3.0 to 3.6 v, vrefh0 = 3.0 v to avcc0, vref = 3.0 v to avcc condition 2: vcc = pllvcc = 2.7 to 3.6 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc condition 3: vcc = pllvcc = 4.0 to 5.5 v, vss = pllvss = avss0 = avss = vrefl0 = 0 v avcc0 = avcc = 4.0 to 5.5 v, vrefh0 = 4.0 v to avcc0, vref = 4.0 v to avcc temperature range for the programming/erasure operation: ta = -40 to +85c. ta is the same under conditions 1 to 3. item symbol min. typ. max. unit test conditions programming time 8 bytes t dp8 -0 . 42m sp c l k = 50 mhz 128 bytes t dp128 -15m s erasure time 2 kbytes t de2k - 70 250 ms pclk = 50 mhz blank check time 8 bytes t dbc8 --3 0 ? sp c l k = 50 mhz 2 kbytes t dbc2k --0 . 7m s rewrite/erase cycle *1 n dpec 30000 *2 --times suspend delay time during writing t dspd - - 120 ? s figure 5.24 pclk = 50 mhz first suspend delay time during erasing (in suspend priority mode) t dsesd1 - - 120 ? s second suspend delay time during erasing (in suspend priority mode) t dsesd2 --1 . 7m s suspend delay time during erasing (in erasure priority mode) t dseed --1 . 7m s data hold time *3 t ddrp 10 - - year
r01ds0096ej0100 rev.1.00 page 87 of 92 apr 20, 2011 rx62t group 5. electrical characteristics figure 5.24 flash memory write/erase suspend timing fcu command fstatr0.frdy write pulse write suspend fcu command fstatr0.frdy erasure pulse erasure suspend in suspend priority mode fcu command fstatr0.frdy erasure pulse erasure suspend in erasure priority mode program suspend ready not ready ready programming t spd erase suspend ready not ready ready t seed erasing erase suspend resume suspend ready not ready ready not ready t sesd1 t sesd2 erasing erasing
r01ds0096ej0100 rev.1.00 page 88 of 92 apr 20, 2011 rx62t group appendix 1. package dimensions appendix 1. package dimensions figure a 112-pin lqfp (plqp0112ja-a) package dimensions x *2 *1 *3 f 112 85 84 57 56 29 28 1 index mark y e z d z e h d d h e b p detail f l c l 1 a 2 a a 1 include trim offset. dimension " *3" does not note) do not include mold flash. dimensions " *1" and " *2" 1. 2. l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 0.65 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 21.8 22.0 22.2 21.8 22.0 22.2 a 2 1.4 e 19.9 20.0 20.1 d 19.9 20.0 20.1 reference symbol dimension in millimeters min nom max 0.27 0.32 0.37 0.09 0.145 0.20 0.13 1.225 1.225 0.30 0.125 1.0 p-lqfp112-20x20-0.65 1.2g mass[typ.] fp-112e / fp-112ev plqp0112ja-a renesas code jeita package code previous code terminal cross section c b p c 1 b 1 e
r01ds0096ej0100 rev.1.00 page 89 of 92 apr 20, 2011 rx62t group appendix 1. package dimensions figure b 100-pin lqfp (plqp0100kb-a) package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. y index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e
r01ds0096ej0100 rev.1.00 page 90 of 92 apr 20, 2011 rx62t group appendix 1. package dimensions figure c 80-pin lqfp (plqp 0080ja-a) package dimensions y *2 *1 *3 f 80 61 60 41 40 21 20 1 x index mark e d h d h e z d z e b p detail f l c a 2 l 1 a a 1 include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. previous code jeita package code renesas code plqp0080ja-a fp-80w / fp-80wv mass[typ.] 0.6g p-lqfp80-14x14-0.65 1.0 0.125 0.30 0.825 0.825 0.13 0.20 0.145 0.09 0.370.320.27 maxnommin dimension in millimeters symbol reference 14.114.013.9 d 14.114.013.9 e 1.4 a 2 16.216.015.8 16.216.015.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.65 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c1 b1 e
r01ds0096ej0100 rev.1.00 page 91 of 92 apr 20, 2011 rx62t group appendix 1. package dimensions figure d 64-pin lqfp (plqp0064kb-a) package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark *3 17 32 64 49 11 6 33 48 f *1 *2 x y b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.250.200.15 maxnommin dimension in millimeters symbol reference 10.110.0 9.9 d 10.110.0 9.9 e 1.4 a 2 12.212.011.8 12.212.011.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e
r01ds0096ej0100 rev.1.00 page 92 of 92 apr 20, 2011 rx62t group revision history revision history rx62t group datasheet rev. date description page summary 1.00 apr 20, 2011 ? first edition issued all trademarks and registered trademarks are the property of thei r respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
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"high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-owned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.1

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